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107 lines
3.7 KiB
107 lines
3.7 KiB
NVIDIA Tegra194 pinmux controller |
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Required properties: |
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- compatible: "nvidia,tegra194-pinmux" |
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- reg: Should contain a list of base address and size pairs for: |
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- first entry: The APB_MISC_GP_*_PADCTRL registers (pad control) |
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- second entry: The PINMUX_AUX_* registers (pinmux) |
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Please refer to pinctrl-bindings.txt in this directory for details of the |
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common pinctrl bindings used by client devices, including the meaning of the |
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phrase "pin configuration node". |
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Tegra's pin configuration nodes act as a container for an arbitrary number of |
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subnodes. Each of these subnodes represents some desired configuration for a |
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pin, a group, or a list of pins or groups. This configuration can include the |
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mux function to select on those pin(s)/group(s), and various pin configuration |
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parameters, such as pull-up, tristate, drive strength, etc. |
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See the TRM to determine which properties and values apply to each pin/group. |
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Macro values for property values are defined in |
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include/dt-binding/pinctrl/pinctrl-tegra.h. |
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Required subnode-properties: |
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- nvidia,pins : An array of strings. Each string contains the name of a pin or |
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group. Valid values for these names are listed below. |
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Optional subnode-properties: |
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- nvidia,function: A string containing the name of the function to mux to the |
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pin or group. |
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- nvidia,pull: Integer, representing the pull-down/up to apply to the pin. |
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0: none, 1: down, 2: up. |
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- nvidia,tristate: Integer. |
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0: drive, 1: tristate. |
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- nvidia,enable-input: Integer. Enable the pin's input path. |
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enable :TEGRA_PIN_ENABLE and |
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disable or output only: TEGRA_PIN_DISABLE. |
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- nvidia,open-drain: Integer. |
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enable: TEGRA_PIN_ENABLE. |
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disable: TEGRA_PIN_DISABLE. |
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- nvidia,lock: Integer. Lock the pin configuration against further changes |
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until reset. |
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enable: TEGRA_PIN_ENABLE. |
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disable: TEGRA_PIN_DISABLE. |
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- nvidia,io-hv: Integer. Select high-voltage receivers. |
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normal: TEGRA_PIN_DISABLE |
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high: TEGRA_PIN_ENABLE |
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- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input. |
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normal: TEGRA_PIN_DISABLE |
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high: TEGRA_PIN_ENABLE |
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- nvidia,drive-type: Integer. Valid range 0...3. |
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- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest. |
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The range of valid values depends on the pingroup. See "CAL_DRVDN" in the |
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Tegra TRM. |
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- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest. |
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The range of valid values depends on the pingroup. See "CAL_DRVUP" in the |
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Tegra TRM. |
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Valid values for pin and group names (nvidia,pin) are: |
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These correspond to Tegra PADCTL_* (pinmux) registers. |
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Mux groups: |
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These correspond to Tegra PADCTL_* (pinmux) registers. Any property |
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that exists in those registers may be set for the following pin names. |
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pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1 |
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Drive groups: |
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These registers controls a single pin for which a mux group exists. |
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See the list above for the pin name to use when configuring the pinmux. |
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pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1 |
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Valid values for nvidia,functions are: |
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pe5 |
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Power Domain: |
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pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 are part of PCIE C5 power |
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partition. Client devices must enable this partition before accessing |
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these pins here. |
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Example: |
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tegra_pinctrl: pinmux: pinmux@2430000 { |
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compatible = "nvidia,tegra194-pinmux"; |
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reg = <0x2430000 0x17000 |
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0xc300000 0x4000>; |
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pinctrl-names = "pex_rst"; |
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pinctrl-0 = <&pex_rst_c5_out_state>; |
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pex_rst_c5_out_state: pex_rst_c5_out { |
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pex_rst { |
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nvidia,pins = "pex_l5_rst_n_pgg1"; |
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nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
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nvidia,lpdr = <TEGRA_PIN_ENABLE>; |
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nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
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nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
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nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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}; |
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}; |
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};
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