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173 lines
5.1 KiB
173 lines
5.1 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6797-pinctrl.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Mediatek MT6797 Pin Controller Device Tree Bindings |
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maintainers: |
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- Sean Wang <[email protected]> |
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description: |+ |
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The MediaTek's MT6797 Pin controller is used to control SoC pins. |
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properties: |
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compatible: |
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const: mediatek,mt6797-pinctrl |
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reg: |
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minItems: 5 |
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maxItems: 5 |
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reg-names: |
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items: |
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- const: gpio |
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- const: iocfgl |
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- const: iocfgb |
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- const: iocfgr |
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- const: iocfgt |
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gpio-controller: true |
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"#gpio-cells": |
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const: 2 |
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description: | |
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Number of cells in GPIO specifier. Since the generic GPIO |
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binding is used, the amount of cells must be specified as 2. See the below |
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mentioned gpio binding representation for description of particular cells. |
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interrupt-controller: true |
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interrupts: |
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maxItems: 1 |
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"#interrupt-cells": |
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const: 2 |
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required: |
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- compatible |
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- reg |
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- reg-names |
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- gpio-controller |
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- "#gpio-cells" |
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patternProperties: |
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'-[0-9]+$': |
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type: object |
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additionalProperties: false |
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patternProperties: |
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'pins': |
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type: object |
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additionalProperties: false |
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description: | |
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A pinctrl node should contain at least one subnodes representing the |
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pinctrl groups available on the machine. Each subnode will list the |
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pins it needs, and how they should be configured, with regard to muxer |
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configuration, pullups, drive strength, input enable/disable and input |
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schmitt. |
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$ref: "/schemas/pinctrl/pincfg-node.yaml" |
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properties: |
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pinmux: |
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description: |
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integer array, represents gpio pin number and mux setting. |
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Supported pin number and mux varies for different SoCs, and are |
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defined as macros in <soc>-pinfunc.h directly. |
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bias-disable: true |
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bias-pull-up: true |
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bias-pull-down: true |
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input-enable: true |
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input-disable: true |
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output-enable: true |
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output-low: true |
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output-high: true |
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input-schmitt-enable: true |
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input-schmitt-disable: true |
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drive-strength: |
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enum: [2, 4, 8, 12, 16] |
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slew-rate: |
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enum: [0, 1] |
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mediatek,pull-up-adv: |
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description: | |
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Pull up setings for 2 pull resistors, R0 and R1. User can |
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configure those special pins. Valid arguments are described as below: |
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0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. |
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1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. |
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2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. |
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3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [0, 1, 2, 3] |
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mediatek,pull-down-adv: |
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description: | |
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Pull down settings for 2 pull resistors, R0 and R1. User can |
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configure those special pins. Valid arguments are described as below: |
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0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. |
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1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. |
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2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. |
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3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [0, 1, 2, 3] |
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mediatek,tdsel: |
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description: | |
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An integer describing the steps for output level shifter duty |
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cycle when asserted (high pulse width adjustment). Valid arguments |
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are from 0 to 15. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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mediatek,rdsel: |
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description: | |
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An integer describing the steps for input level shifter duty cycle |
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when asserted (high pulse width adjustment). Valid arguments are |
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from 0 to 63. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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required: |
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- pinmux |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/interrupt-controller/irq.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/pinctrl/mt6797-pinfunc.h> |
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soc { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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pio: pinctrl@10005000 { |
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compatible = "mediatek,mt6797-pinctrl"; |
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reg = <0 0x10005000 0 0x1000>, |
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<0 0x10002000 0 0x400>, |
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<0 0x10002400 0 0x400>, |
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<0 0x10002800 0 0x400>, |
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<0 0x10002C00 0 0x400>; |
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reg-names = "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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uart_pins_a: uart-0 { |
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pins1 { |
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pinmux = <MT6797_GPIO232__FUNC_URXD1>, |
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<MT6797_GPIO233__FUNC_UTXD1>; |
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}; |
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}; |
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}; |
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};
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