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206 lines
5.7 KiB
206 lines
5.7 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Mediatek MT65xx Pin Controller Device Tree Bindings |
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maintainers: |
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- Sean Wang <[email protected]> |
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description: |+ |
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The Mediatek's Pin controller is used to control SoC pins. |
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properties: |
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compatible: |
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enum: |
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- mediatek,mt2701-pinctrl |
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- mediatek,mt2712-pinctrl |
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- mediatek,mt6397-pinctrl |
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- mediatek,mt7623-pinctrl |
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- mediatek,mt8127-pinctrl |
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- mediatek,mt8135-pinctrl |
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- mediatek,mt8167-pinctrl |
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- mediatek,mt8173-pinctrl |
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- mediatek,mt8516-pinctrl |
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reg: |
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maxItems: 1 |
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pins-are-numbered: |
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$ref: /schemas/types.yaml#/definitions/flag |
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description: | |
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Specify the subnodes are using numbered pinmux to specify pins. |
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gpio-controller: true |
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"#gpio-cells": |
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const: 2 |
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description: | |
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Number of cells in GPIO specifier. Since the generic GPIO |
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binding is used, the amount of cells must be specified as 2. See the below |
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mentioned gpio binding representation for description of particular cells. |
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mediatek,pctl-regmap: |
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$ref: /schemas/types.yaml#/definitions/phandle-array |
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minItems: 1 |
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maxItems: 2 |
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description: | |
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Should be phandles of the syscfg node. |
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interrupt-controller: true |
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interrupts: |
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minItems: 1 |
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maxItems: 3 |
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"#interrupt-cells": |
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const: 2 |
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required: |
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- compatible |
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- pins-are-numbered |
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- gpio-controller |
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- "#gpio-cells" |
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patternProperties: |
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'-[0-9]+$': |
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type: object |
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additionalProperties: false |
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patternProperties: |
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'pins': |
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type: object |
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additionalProperties: false |
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description: | |
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A pinctrl node should contain at least one subnodes representing the |
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pinctrl groups available on the machine. Each subnode will list the |
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pins it needs, and how they should be configured, with regard to muxer |
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configuration, pullups, drive strength, input enable/disable and input |
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schmitt. |
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$ref: "/schemas/pinctrl/pincfg-node.yaml" |
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properties: |
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pinmux: |
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description: |
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integer array, represents gpio pin number and mux setting. |
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Supported pin number and mux varies for different SoCs, and are |
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defined as macros in <soc>-pinfunc.h directly. |
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bias-disable: true |
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bias-pull-up: |
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description: | |
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Besides generic pinconfig options, it can be used as the pull up |
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settings for 2 pull resistors, R0 and R1. User can configure those |
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special pins. Some macros have been defined for this usage, such |
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as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for |
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valid arguments. |
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bias-pull-down: true |
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input-enable: true |
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input-disable: true |
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output-low: true |
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output-high: true |
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input-schmitt-enable: true |
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input-schmitt-disable: true |
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drive-strength: |
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description: | |
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Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, |
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etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments. |
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required: |
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- pinmux |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/interrupt-controller/irq.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/pinctrl/mt8135-pinfunc.h> |
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soc { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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syscfg_pctl_a: syscfg-pctl-a@10005000 { |
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compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; |
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reg = <0 0x10005000 0 0x1000>; |
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}; |
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syscfg_pctl_b: syscfg-pctl-b@1020c020 { |
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compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; |
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reg = <0 0x1020C020 0 0x1000>; |
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}; |
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pinctrl@1c20800 { |
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compatible = "mediatek,mt8135-pinctrl"; |
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reg = <0 0x1000B000 0 0x1000>; |
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mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>; |
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pins-are-numbered; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; |
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i2c0_pins_a: i2c0-0 { |
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pins1 { |
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pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>, |
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<MT8135_PIN_101_SCL0__FUNC_SCL0>; |
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bias-disable; |
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}; |
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}; |
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i2c1_pins_a: i2c1-0 { |
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pins { |
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pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>, |
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<MT8135_PIN_196_SCL1__FUNC_SCL1>; |
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>; |
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}; |
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}; |
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i2c2_pins_a: i2c2-0 { |
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pins1 { |
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pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>; |
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bias-pull-down; |
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}; |
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pins2 { |
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pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>; |
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bias-pull-up; |
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}; |
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}; |
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i2c3_pins_a: i2c3-0 { |
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pins1 { |
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pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>, |
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<MT8135_PIN_41_DAC_WS__FUNC_GPIO41>; |
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>; |
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}; |
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pins2 { |
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pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>, |
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<MT8135_PIN_36_SDA3__FUNC_SDA3>; |
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output-low; |
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>; |
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}; |
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pins3 { |
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pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>, |
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<MT8135_PIN_60_JTDI__FUNC_JTDI>; |
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drive-strength = <32>; |
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}; |
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}; |
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}; |
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};
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