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176 lines
5.4 KiB
176 lines
5.4 KiB
* Atmel AT91 Pinmux Controller |
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The AT91 Pinmux Controller, enables the IC |
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to share one PAD to several functional blocks. The sharing is done by |
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multiplexing the PAD input/output signals. For each PAD there are up to |
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8 muxing options (called periph modes). Since different modules require |
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different PAD settings (like pull up, keeper, etc) the controller controls |
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also the PAD settings parameters. |
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Please refer to pinctrl-bindings.txt in this directory for details of the |
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common pinctrl bindings used by client devices, including the meaning of the |
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phrase "pin configuration node". |
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Atmel AT91 pin configuration node is a node of a group of pins which can be |
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used for a specific device or function. This node represents both mux and config |
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of the pins in that group. The 'pins' selects the function mode(also named pin |
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mode) this pin can work on and the 'config' configures various pad settings |
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such as pull-up, multi drive, etc. |
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Required properties for iomux controller: |
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- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl" |
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or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl" |
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- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be |
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configured in this periph mode. All the periph and bank need to be describe. |
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How to create such array: |
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Each column will represent the possible peripheral of the pinctrl |
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Each line will represent a pio bank |
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Take an example on the 9260 |
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Peripheral: 2 ( A and B) |
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Bank: 3 (A, B and C) |
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=> |
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/* A B */ |
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0xffffffff 0xffc00c3b /* pioA */ |
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0xffffffff 0x7fff3ccf /* pioB */ |
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0xffffffff 0x007fffff /* pioC */ |
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For each peripheral/bank we will describe in a u32 if a pin can be |
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configured in it by putting 1 to the pin bit (1 << pin) |
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Let's take the pioA on peripheral B |
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From the datasheet Table 10-2. |
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Peripheral B |
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PA0 MCDB0 |
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PA1 MCCDB |
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PA2 |
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PA3 MCDB3 |
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PA4 MCDB2 |
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PA5 MCDB1 |
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PA6 |
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PA7 |
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PA8 |
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PA9 |
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PA10 ETX2 |
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PA11 ETX3 |
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PA12 |
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PA13 |
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PA14 |
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PA15 |
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PA16 |
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PA17 |
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PA18 |
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PA19 |
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PA20 |
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PA21 |
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PA22 ETXER |
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PA23 ETX2 |
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PA24 ETX3 |
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PA25 ERX2 |
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PA26 ERX3 |
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PA27 ERXCK |
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PA28 ECRS |
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PA29 ECOL |
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PA30 RXD4 |
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PA31 TXD4 |
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=> 0xffc00c3b |
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Required properties for pin configuration node: |
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- atmel,pins: 4 integers array, represents a group of pins mux and config |
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setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>. |
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The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B... |
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PIN_BANK 0 is pioA, PIN_BANK 1 is pioB... |
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Bits used for CONFIG: |
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PULL_UP (1 << 0): indicate this pin needs a pull up. |
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MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive. |
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Multi-drive is equivalent to open-drain type output. |
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DEGLITCH (1 << 2): indicate this pin needs deglitch. |
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PULL_DOWN (1 << 3): indicate this pin needs a pull down. |
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DIS_SCHMIT (1 << 4): indicate this pin needs to the disable schmitt trigger. |
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DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the |
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following values: |
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00 - No change (reset state value kept) |
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01 - Low |
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10 - Medium |
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11 - High |
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OUTPUT (1 << 7): indicate this pin need to be configured as an output. |
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OUTPUT_VAL (1 << 8): output val (1 = high, 0 = low) |
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SLEWRATE (1 << 9): slew rate of the pin: 0 = disable, 1 = enable |
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DEBOUNCE (1 << 16): indicate this pin needs debounce. |
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DEBOUNCE_VAL (0x3fff << 17): debounce value. |
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NOTE: |
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Some requirements for using atmel,at91rm9200-pinctrl binding: |
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1. We have pin function node defined under at91 controller node to represent |
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what pinmux functions this SoC supports. |
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2. The driver can use the function node's name and pin configuration node's |
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name describe the pin function and group hierarchy. |
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For example, Linux at91 pinctrl driver takes the function node's name |
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as the function name and pin configuration node's name as group name to |
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create the map table. |
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3. Each pin configuration node should have a phandle, devices can set pins |
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configurations by referring to the phandle of that pin configuration node. |
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4. The gpio controller must be describe in the pinctrl simple-bus. |
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For each bank the required properties are: |
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- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or |
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"microchip,sam9x60-gpio" |
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- reg: physical base address and length of the controller's registers |
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- interrupts: interrupt outputs from the controller |
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- interrupt-controller: marks the device node as an interrupt controller |
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- #interrupt-cells: should be 2; refer to ../interrupt-controller/interrupts.txt |
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for more details. |
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- gpio-controller |
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- #gpio-cells: should be 2; the first cell is the GPIO number and the second |
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cell specifies GPIO flags as defined in <dt-bindings/gpio/gpio.h>. |
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- clocks: bank clock |
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Examples: |
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pinctrl@fffff400 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; |
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reg = <0xfffff400 0x600>; |
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pioA: gpio@fffff400 { |
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compatible = "atmel,at91sam9x5-gpio"; |
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reg = <0xfffff400 0x200>; |
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; |
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}; |
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atmel,mux-mask = < |
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/* A B */ |
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0xffffffff 0xffc00c3b /* pioA */ |
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0xffffffff 0x7fff3ccf /* pioB */ |
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0xffffffff 0x007fffff /* pioC */ |
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>; |
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/* shared pinctrl settings */ |
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dbgu { |
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pinctrl_dbgu: dbgu-0 { |
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atmel,pins = |
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<1 14 0x1 0x0 /* PB14 periph A */ |
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1 15 0x1 0x1>; /* PB15 periph A with pullup */ |
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}; |
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}; |
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}; |
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dbgu: serial@fffff200 { |
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compatible = "atmel,at91sam9260-usart"; |
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reg = <0xfffff200 0x200>; |
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interrupts = <1 4 7>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_dbgu>; |
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};
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