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28 lines
875 B
28 lines
875 B
NVIDIA Tegra194 P2U binding |
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Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High |
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Speed) each interfacing with 12 and 8 P2U instances respectively. |
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A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE |
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interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe |
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lane. |
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Required properties: |
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- compatible: For Tegra19x, must contain "nvidia,tegra194-p2u". |
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- reg: Should be the physical address space and length of respective each P2U |
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instance. |
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- reg-names: Must include the entry "ctl". |
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Required properties for PHY port node: |
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- #phy-cells: Defined by generic PHY bindings. Must be 0. |
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Refer to phy/phy-bindings.txt for the generic PHY binding properties. |
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Example: |
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p2u_hsio_0: phy@3e10000 { |
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compatible = "nvidia,tegra194-p2u"; |
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reg = <0x03e10000 0x10000>; |
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reg-names = "ctl"; |
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#phy-cells = <0>; |
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};
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