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88 lines
1.9 KiB
88 lines
1.9 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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# Copyright (c) 2020 MediaTek |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: MediaTek MIPI Display Serial Interface (DSI) PHY binding |
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maintainers: |
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- Chun-Kuang Hu <[email protected]> |
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- Philipp Zabel <[email protected]> |
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- Chunfeng Yun <[email protected]> |
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description: The MIPI DSI PHY supports up to 4-lane output. |
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properties: |
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$nodename: |
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pattern: "^dsi-phy@[0-9a-f]+$" |
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compatible: |
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oneOf: |
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- items: |
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- enum: |
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- mediatek,mt7623-mipi-tx |
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- const: mediatek,mt2701-mipi-tx |
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- const: mediatek,mt2701-mipi-tx |
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- const: mediatek,mt8173-mipi-tx |
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- const: mediatek,mt8183-mipi-tx |
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reg: |
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maxItems: 1 |
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clocks: |
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items: |
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- description: PLL reference clock |
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clock-output-names: |
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maxItems: 1 |
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"#phy-cells": |
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const: 0 |
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"#clock-cells": |
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const: 0 |
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nvmem-cells: |
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maxItems: 1 |
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description: A phandle to the calibration data provided by a nvmem device, |
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if unspecified, default values shall be used. |
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nvmem-cell-names: |
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items: |
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- const: calibration-data |
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drive-strength-microamp: |
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description: adjust driving current |
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multipleOf: 200 |
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minimum: 2000 |
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maximum: 6000 |
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default: 4600 |
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required: |
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- compatible |
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- reg |
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- clocks |
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- clock-output-names |
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- "#phy-cells" |
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- "#clock-cells" |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/mt8173-clk.h> |
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dsi-phy@10215000 { |
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compatible = "mediatek,mt8173-mipi-tx"; |
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reg = <0x10215000 0x1000>; |
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clocks = <&clk26m>; |
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clock-output-names = "mipi_tx0_pll"; |
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drive-strength-microamp = <4000>; |
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nvmem-cells= <&mipi_tx_calibration>; |
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nvmem-cell-names = "calibration-data"; |
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#clock-cells = <0>; |
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#phy-cells = <0>; |
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}; |
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...
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