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128 lines
3.4 KiB
128 lines
3.4 KiB
# SPDX-License-Identifier: GPL-2.0 |
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%YAML 1.2 |
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--- |
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$id: "http://devicetree.org/schemas/net/rockchip-dwmac.yaml#" |
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$schema: "http://devicetree.org/meta-schemas/core.yaml#" |
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title: Rockchip 10/100/1000 Ethernet driver(GMAC) |
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maintainers: |
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- David Wu <[email protected]> |
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# We need a select here so we don't match all nodes with 'snps,dwmac' |
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select: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- rockchip,px30-gmac |
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- rockchip,rk3128-gmac |
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- rockchip,rk3228-gmac |
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- rockchip,rk3288-gmac |
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- rockchip,rk3308-gmac |
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- rockchip,rk3328-gmac |
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- rockchip,rk3366-gmac |
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- rockchip,rk3368-gmac |
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- rockchip,rk3399-gmac |
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- rockchip,rk3568-gmac |
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- rockchip,rv1108-gmac |
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required: |
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- compatible |
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allOf: |
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- $ref: "snps,dwmac.yaml#" |
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properties: |
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compatible: |
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oneOf: |
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- items: |
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- enum: |
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- rockchip,px30-gmac |
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- rockchip,rk3128-gmac |
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- rockchip,rk3228-gmac |
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- rockchip,rk3288-gmac |
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- rockchip,rk3308-gmac |
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- rockchip,rk3328-gmac |
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- rockchip,rk3366-gmac |
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- rockchip,rk3368-gmac |
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- rockchip,rk3399-gmac |
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- rockchip,rv1108-gmac |
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- items: |
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- enum: |
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- rockchip,rk3568-gmac |
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- const: snps,dwmac-4.20a |
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clocks: |
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minItems: 5 |
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maxItems: 8 |
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clock-names: |
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contains: |
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enum: |
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- stmmaceth |
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- mac_clk_tx |
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- mac_clk_rx |
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- aclk_mac |
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- pclk_mac |
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- clk_mac_ref |
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- clk_mac_refout |
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- clk_mac_speed |
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clock_in_out: |
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description: |
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For RGMII, it must be "input", means main clock(125MHz) |
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is not sourced from SoC's PLL, but input from PHY. |
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For RMII, "input" means PHY provides the reference clock(50MHz), |
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"output" means GMAC provides the reference clock. |
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$ref: /schemas/types.yaml#/definitions/string |
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enum: [input, output] |
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rockchip,grf: |
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description: The phandle of the syscon node for the general register file. |
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$ref: /schemas/types.yaml#/definitions/phandle |
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tx_delay: |
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description: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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rx_delay: |
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description: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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phy-supply: |
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description: PHY regulator |
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required: |
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- compatible |
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- clocks |
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- clock-names |
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unevaluatedProperties: false |
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examples: |
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- | |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/clock/rk3288-cru.h> |
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gmac: ethernet@ff290000 { |
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compatible = "rockchip,rk3288-gmac"; |
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reg = <0xff290000 0x10000>; |
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "macirq"; |
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clocks = <&cru SCLK_MAC>, |
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<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, |
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<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, |
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<&cru ACLK_GMAC>, <&cru PCLK_GMAC>; |
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clock-names = "stmmaceth", |
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"mac_clk_rx", "mac_clk_tx", |
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"clk_mac_ref", "clk_mac_refout", |
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"aclk_mac", "pclk_mac"; |
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assigned-clocks = <&cru SCLK_MAC>; |
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assigned-clock-parents = <&ext_gmac>; |
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rockchip,grf = <&grf>; |
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phy-mode = "rgmii"; |
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clock_in_out = "input"; |
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tx_delay = <0x30>; |
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rx_delay = <0x10>; |
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};
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