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139 lines
3.8 KiB
139 lines
3.8 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/net/can/renesas,rcar-can.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Renesas R-Car CAN Controller |
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maintainers: |
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- Sergei Shtylyov <[email protected]> |
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properties: |
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compatible: |
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oneOf: |
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- items: |
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- enum: |
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- renesas,can-r8a7778 # R-Car M1-A |
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- renesas,can-r8a7779 # R-Car H1 |
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- const: renesas,rcar-gen1-can # R-Car Gen1 |
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- items: |
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- enum: |
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- renesas,can-r8a7742 # RZ/G1H |
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- renesas,can-r8a7743 # RZ/G1M |
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- renesas,can-r8a7744 # RZ/G1N |
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- renesas,can-r8a7745 # RZ/G1E |
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- renesas,can-r8a77470 # RZ/G1C |
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- renesas,can-r8a7790 # R-Car H2 |
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- renesas,can-r8a7791 # R-Car M2-W |
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- renesas,can-r8a7792 # R-Car V2H |
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- renesas,can-r8a7793 # R-Car M2-N |
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- renesas,can-r8a7794 # R-Car E2 |
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- const: renesas,rcar-gen2-can # R-Car Gen2 and RZ/G1 |
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- items: |
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- enum: |
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- renesas,can-r8a774a1 # RZ/G2M |
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- renesas,can-r8a774b1 # RZ/G2N |
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- renesas,can-r8a774c0 # RZ/G2E |
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- renesas,can-r8a774e1 # RZ/G2H |
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- renesas,can-r8a7795 # R-Car H3 |
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- renesas,can-r8a7796 # R-Car M3-W |
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- renesas,can-r8a77961 # R-Car M3-W+ |
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- renesas,can-r8a77965 # R-Car M3-N |
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- renesas,can-r8a77990 # R-Car E3 |
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- renesas,can-r8a77995 # R-Car D3 |
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- const: renesas,rcar-gen3-can # R-Car Gen3 and RZ/G2 |
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reg: |
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maxItems: 1 |
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interrupts: |
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maxItems: 1 |
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clocks: |
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maxItems: 3 |
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clock-names: |
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items: |
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- const: clkp1 |
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- const: clkp2 |
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- const: can_clk |
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power-domains: |
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maxItems: 1 |
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resets: |
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maxItems: 1 |
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renesas,can-clock-select: |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [ 0, 1, 3 ] |
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default: 0 |
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description: | |
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R-Car CAN Clock Source Select. Valid values are: |
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<0x0> (default) : Peripheral clock (clkp1) |
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<0x1> : Peripheral clock (clkp2) |
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<0x3> : External input clock |
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assigned-clocks: |
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description: |
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Reference to the clkp2 (CANFD) clock. |
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On R-Car Gen3 and RZ/G2 SoCs, "clkp2" is the CANFD clock. This is a div6 |
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clock and can be used by both CAN and CAN FD controllers at the same |
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time. It needs to be scaled to maximum frequency if any of these |
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controllers use it. |
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assigned-clock-rates: |
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description: Maximum frequency of the CANFD clock. |
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required: |
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- compatible |
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- reg |
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- interrupts |
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- clocks |
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- clock-names |
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- power-domains |
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allOf: |
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- $ref: can-controller.yaml# |
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- if: |
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not: |
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properties: |
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compatible: |
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contains: |
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const: renesas,rcar-gen1-can |
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then: |
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required: |
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- resets |
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- if: |
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properties: |
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compatible: |
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contains: |
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const: renesas,rcar-gen3-can |
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then: |
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required: |
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- assigned-clocks |
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- assigned-clock-rates |
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unevaluatedProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/r8a7791-cpg-mssr.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/power/r8a7791-sysc.h> |
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can0: can@e6e80000 { |
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compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; |
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reg = <0xe6e80000 0x1000>; |
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&cpg CPG_MOD 916>, |
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<&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; |
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clock-names = "clkp1", "clkp2", "can_clk"; |
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power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; |
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resets = <&cpg 916>; |
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};
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