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47 lines
1.4 KiB
47 lines
1.4 KiB
Hisilicon Hip04 Soc NAND controller DT binding |
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Required properties: |
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- compatible: Should be "hisilicon,504-nfc". |
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- reg: The first contains base physical address and size of |
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NAND controller's registers. The second contains base |
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physical address and size of NAND controller's buffer. |
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- interrupts: Interrupt number for nfc. |
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- nand-bus-width: See nand-controller.yaml. |
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- nand-ecc-mode: Support none and hw ecc mode. |
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- #address-cells: Partition address, should be set 1. |
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- #size-cells: Partition size, should be set 1. |
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Optional properties: |
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- nand-ecc-strength: Number of bits to correct per ECC step. |
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- nand-ecc-step-size: Number of data bytes covered by a single ECC step. |
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The following ECC strength and step size are currently supported: |
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- nand-ecc-strength = <16>, nand-ecc-step-size = <1024> |
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Flash chip may optionally contain additional sub-nodes describing partitions of |
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the address space. See partition.txt for more detail. |
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Example: |
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nand: nand@4020000 { |
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compatible = "hisilicon,504-nfc"; |
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reg = <0x4020000 0x10000>, <0x5000000 0x1000>; |
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interrupts = <0 379 4>; |
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nand-bus-width = <8>; |
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nand-ecc-mode = "hw"; |
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nand-ecc-strength = <16>; |
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nand-ecc-step-size = <1024>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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partition@0 { |
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label = "nand_text"; |
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reg = <0x00000000 0x00400000>; |
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}; |
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... |
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};
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