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24 lines
670 B
24 lines
670 B
I2C for Hisilicon hix5hd2 chipset platform |
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Required properties: |
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- compatible: Must be "hisilicon,hix5hd2-i2c" |
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- reg: physical base address of the controller and length of memory mapped |
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region. |
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- interrupts: interrupt number to the cpu. |
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- #address-cells = <1>; |
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- #size-cells = <0>; |
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- clocks: phandles to input clocks. |
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Optional properties: |
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- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 |
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- Child nodes conforming to i2c bus binding |
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Examples: |
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I2C0@f8b10000 { |
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compatible = "hisilicon,hix5hd2-i2c"; |
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reg = <0xf8b10000 0x1000>; |
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interrupts = <0 38 4>; |
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clocks = <&clock HIX5HD2_I2C0_RST>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}
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