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54 lines
2.0 KiB
54 lines
2.0 KiB
Xilinx LogiCORE Partial Reconfig Decoupler Softcore |
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The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more |
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decouplers / fpga bridges. |
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The controller can decouple/disable the bridges which prevents signal |
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changes from passing through the bridge. The controller can also |
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couple / enable the bridges which allows traffic to pass through the |
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bridge normally. |
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Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager |
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Softcore is compatible with the Xilinx LogiCORE pr-decoupler. |
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The Dynamic Function eXchange AXI shutdown manager prevents AXI traffic |
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from passing through the bridge. The controller safely handles AXI4MM |
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and AXI4-Lite interfaces on a Reconfigurable Partition when it is |
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undergoing dynamic reconfiguration, preventing the system deadlock |
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that can occur if AXI transactions are interrupted by DFX |
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The Driver supports only MMIO handling. A PR region can have multiple |
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PR Decouplers which can be handled independently or chained via decouple/ |
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decouple_status signals. |
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Required properties: |
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- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by |
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"xlnx,pr-decoupler" or |
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"xlnx,dfx-axi-shutdown-manager-1.00" followed by |
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"xlnx,dfx-axi-shutdown-manager" |
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- regs : base address and size for decoupler module |
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- clocks : input clock to IP |
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- clock-names : should contain "aclk" |
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See Documentation/devicetree/bindings/fpga/fpga-region.txt and |
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Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings. |
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Example: |
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Partial Reconfig Decoupler: |
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fpga-bridge@100000450 { |
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compatible = "xlnx,pr-decoupler-1.00", |
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"xlnx-pr-decoupler"; |
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regs = <0x10000045 0x10>; |
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clocks = <&clkc 15>; |
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clock-names = "aclk"; |
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bridge-enable = <0>; |
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}; |
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Dynamic Function eXchange AXI shutdown manager: |
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fpga-bridge@100000450 { |
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compatible = "xlnx,dfx-axi-shutdown-manager-1.00", |
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"xlnx,dfx-axi-shutdown-manager"; |
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regs = <0x10000045 0x10>; |
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clocks = <&clkc 15>; |
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clock-names = "aclk"; |
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bridge-enable = <0>; |
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};
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