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29 lines
988 B
29 lines
988 B
Altera Passive Serial SPI FPGA Manager |
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Altera FPGAs support a method of loading the bitstream over what is |
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referred to as "passive serial". |
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The passive serial link is not technically SPI, and might require extra |
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circuits in order to play nicely with other SPI slaves on the same bus. |
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See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf |
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Required properties: |
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- compatible: Must be one of the following: |
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"altr,fpga-passive-serial", |
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"altr,fpga-arria10-passive-serial" |
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- reg: SPI chip select of the FPGA |
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- nconfig-gpios: config pin (referred to as nCONFIG in the manual) |
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- nstat-gpios: status pin (referred to as nSTATUS in the manual) |
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Optional properties: |
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- confd-gpios: confd pin (referred to as CONF_DONE in the manual) |
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Example: |
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fpga: fpga@0 { |
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compatible = "altr,fpga-passive-serial"; |
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spi-max-frequency = <20000000>; |
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reg = <0>; |
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nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; |
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nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; |
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confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; |
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};
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