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243 lines
5.5 KiB
243 lines
5.5 KiB
Binding for MediaTek's CPUFreq driver |
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===================================== |
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Required properties: |
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- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. |
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- clock-names: Should contain the following: |
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"cpu" - The multiplexer for clock input of CPU cluster. |
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"intermediate" - A parent of "cpu" clock which is used as "intermediate" clock |
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source (usually MAINPLL) when the original CPU PLL is under |
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transition and not stable yet. |
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Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for |
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generic clock consumer properties. |
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- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml |
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for detail. |
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- proc-supply: Regulator for Vproc of CPU cluster. |
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Optional properties: |
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- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver |
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needs to do "voltage tracking" to step by step scale up/down Vproc and |
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Vsram to fit SoC specific needs. When absent, the voltage scaling |
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flow is handled by hardware, hence no software "voltage tracking" is |
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needed. |
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- #cooling-cells: |
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For details, please refer to |
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Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml |
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Example 1 (MT7623 SoC): |
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cpu_opp_table: opp_table { |
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compatible = "operating-points-v2"; |
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opp-shared; |
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opp-598000000 { |
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opp-hz = /bits/ 64 <598000000>; |
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opp-microvolt = <1050000>; |
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}; |
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opp-747500000 { |
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opp-hz = /bits/ 64 <747500000>; |
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opp-microvolt = <1050000>; |
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}; |
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opp-1040000000 { |
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opp-hz = /bits/ 64 <1040000000>; |
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opp-microvolt = <1150000>; |
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}; |
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opp-1196000000 { |
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opp-hz = /bits/ 64 <1196000000>; |
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opp-microvolt = <1200000>; |
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}; |
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opp-1300000000 { |
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opp-hz = /bits/ 64 <1300000000>; |
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opp-microvolt = <1300000>; |
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}; |
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}; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a7"; |
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reg = <0x0>; |
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clocks = <&infracfg CLK_INFRA_CPUSEL>, |
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<&apmixedsys CLK_APMIXED_MAINPLL>; |
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clock-names = "cpu", "intermediate"; |
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operating-points-v2 = <&cpu_opp_table>; |
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#cooling-cells = <2>; |
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}; |
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cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a7"; |
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reg = <0x1>; |
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operating-points-v2 = <&cpu_opp_table>; |
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}; |
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cpu@2 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a7"; |
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reg = <0x2>; |
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operating-points-v2 = <&cpu_opp_table>; |
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}; |
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cpu@3 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a7"; |
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reg = <0x3>; |
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operating-points-v2 = <&cpu_opp_table>; |
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}; |
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Example 2 (MT8173 SoC): |
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cpu_opp_table_a: opp_table_a { |
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compatible = "operating-points-v2"; |
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opp-shared; |
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opp-507000000 { |
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opp-hz = /bits/ 64 <507000000>; |
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opp-microvolt = <859000>; |
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}; |
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opp-702000000 { |
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opp-hz = /bits/ 64 <702000000>; |
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opp-microvolt = <908000>; |
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}; |
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opp-1001000000 { |
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opp-hz = /bits/ 64 <1001000000>; |
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opp-microvolt = <983000>; |
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}; |
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opp-1105000000 { |
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opp-hz = /bits/ 64 <1105000000>; |
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opp-microvolt = <1009000>; |
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}; |
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opp-1183000000 { |
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opp-hz = /bits/ 64 <1183000000>; |
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opp-microvolt = <1028000>; |
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}; |
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opp-1404000000 { |
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opp-hz = /bits/ 64 <1404000000>; |
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opp-microvolt = <1083000>; |
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}; |
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opp-1508000000 { |
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opp-hz = /bits/ 64 <1508000000>; |
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opp-microvolt = <1109000>; |
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}; |
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opp-1573000000 { |
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opp-hz = /bits/ 64 <1573000000>; |
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opp-microvolt = <1125000>; |
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}; |
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}; |
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cpu_opp_table_b: opp_table_b { |
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compatible = "operating-points-v2"; |
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opp-shared; |
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opp-507000000 { |
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opp-hz = /bits/ 64 <507000000>; |
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opp-microvolt = <828000>; |
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}; |
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opp-702000000 { |
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opp-hz = /bits/ 64 <702000000>; |
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opp-microvolt = <867000>; |
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}; |
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opp-1001000000 { |
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opp-hz = /bits/ 64 <1001000000>; |
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opp-microvolt = <927000>; |
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}; |
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opp-1209000000 { |
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opp-hz = /bits/ 64 <1209000000>; |
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opp-microvolt = <968000>; |
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}; |
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opp-1404000000 { |
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opp-hz = /bits/ 64 <1007000000>; |
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opp-microvolt = <1028000>; |
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}; |
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opp-1612000000 { |
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opp-hz = /bits/ 64 <1612000000>; |
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opp-microvolt = <1049000>; |
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}; |
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opp-1807000000 { |
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opp-hz = /bits/ 64 <1807000000>; |
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opp-microvolt = <1089000>; |
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}; |
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opp-1989000000 { |
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opp-hz = /bits/ 64 <1989000000>; |
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opp-microvolt = <1125000>; |
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}; |
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}; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x000>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CPU_SLEEP_0>; |
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clocks = <&infracfg CLK_INFRA_CA53SEL>, |
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<&apmixedsys CLK_APMIXED_MAINPLL>; |
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clock-names = "cpu", "intermediate"; |
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operating-points-v2 = <&cpu_opp_table_a>; |
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}; |
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cpu1: cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x001>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CPU_SLEEP_0>; |
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clocks = <&infracfg CLK_INFRA_CA53SEL>, |
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<&apmixedsys CLK_APMIXED_MAINPLL>; |
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clock-names = "cpu", "intermediate"; |
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operating-points-v2 = <&cpu_opp_table_a>; |
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}; |
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cpu2: cpu@100 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a72"; |
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reg = <0x100>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CPU_SLEEP_0>; |
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clocks = <&infracfg CLK_INFRA_CA72SEL>, |
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<&apmixedsys CLK_APMIXED_MAINPLL>; |
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clock-names = "cpu", "intermediate"; |
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operating-points-v2 = <&cpu_opp_table_b>; |
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}; |
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cpu3: cpu@101 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a72"; |
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reg = <0x101>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CPU_SLEEP_0>; |
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clocks = <&infracfg CLK_INFRA_CA72SEL>, |
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<&apmixedsys CLK_APMIXED_MAINPLL>; |
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clock-names = "cpu", "intermediate"; |
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operating-points-v2 = <&cpu_opp_table_b>; |
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}; |
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&cpu0 { |
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proc-supply = <&mt6397_vpca15_reg>; |
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}; |
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&cpu1 { |
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proc-supply = <&mt6397_vpca15_reg>; |
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}; |
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&cpu2 { |
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proc-supply = <&da9211_vcpu_reg>; |
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sram-supply = <&mt6397_vsramca7_reg>; |
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}; |
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&cpu3 { |
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proc-supply = <&da9211_vcpu_reg>; |
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sram-supply = <&mt6397_vsramca7_reg>; |
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};
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