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70 lines
1.7 KiB
70 lines
1.7 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: MediaTek's CPUFREQ Bindings |
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maintainers: |
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- Hector Yuan <[email protected]> |
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description: |
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CPUFREQ HW is a hardware engine used by MediaTek SoCs to |
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manage frequency in hardware. It is capable of controlling |
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frequency for multiple clusters. |
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properties: |
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compatible: |
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const: mediatek,cpufreq-hw |
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reg: |
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minItems: 1 |
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maxItems: 2 |
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description: |
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Addresses and sizes for the memory of the HW bases in |
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each frequency domain. Each entry corresponds to |
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a register bank for each frequency domain present. |
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"#performance-domain-cells": |
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description: |
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Number of cells in a performance domain specifier. |
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Set const to 1 here for nodes providing multiple |
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performance domains. |
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const: 1 |
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required: |
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- compatible |
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- reg |
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- "#performance-domain-cells" |
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additionalProperties: false |
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examples: |
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- | |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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enable-method = "psci"; |
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performance-domains = <&performance 0>; |
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reg = <0x000>; |
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}; |
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}; |
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/* ... */ |
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soc { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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performance: performance-controller@11bc00 { |
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compatible = "mediatek,cpufreq-hw"; |
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reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; |
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#performance-domain-cells = <1>; |
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}; |
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};
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