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242 lines
7.7 KiB
242 lines
7.7 KiB
# SPDX-License-Identifier: GPL-2.0 |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/arm/l2c2x0.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: ARM L2 Cache Controller |
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maintainers: |
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- Rob Herring <[email protected]> |
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description: |+ |
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ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/ |
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PL220/PL310 and variants) based level 2 cache controller. All these various |
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implementations of the L2 cache controller have compatible programming |
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models (Note 1). Some of the properties that are just prefixed "cache-*" are |
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taken from section 3.7.3 of the Devicetree Specification which can be found |
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at: |
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https://www.devicetree.org/specifications/ |
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Note 1: The description in this document doesn't apply to integrated L2 |
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cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These |
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integrated L2 controllers are assumed to be all preconfigured by |
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early secure boot code. Thus no need to deal with their configuration |
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in the kernel at all. |
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allOf: |
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- $ref: /schemas/cache-controller.yaml# |
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properties: |
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compatible: |
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oneOf: |
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- enum: |
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- arm,pl310-cache |
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- arm,l220-cache |
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- arm,l210-cache |
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# DEPRECATED by "brcm,bcm11351-a2-pl310-cache" |
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- bcm,bcm11351-a2-pl310-cache |
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# For Broadcom bcm11351 chipset where an |
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# offset needs to be added to the address before passing down to the L2 |
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# cache controller |
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- brcm,bcm11351-a2-pl310-cache |
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# Marvell Controller designed to be |
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# compatible with the ARM one, with system cache mode (meaning |
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# maintenance operations on L1 are broadcasted to the L2 and L2 |
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# performs the same operation). |
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- marvell,aurora-system-cache |
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# Marvell Controller designed to be |
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# compatible with the ARM one with outer cache mode. |
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- marvell,aurora-outer-cache |
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- items: |
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# Marvell Tauros3 cache controller, compatible |
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# with arm,pl310-cache controller. |
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- const: marvell,tauros3-cache |
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- const: arm,pl310-cache |
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cache-level: |
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const: 2 |
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cache-unified: true |
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cache-size: true |
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cache-sets: true |
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cache-block-size: true |
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cache-line-size: true |
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reg: |
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maxItems: 1 |
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arm,data-latency: |
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description: Cycles of latency for Data RAM accesses. Specifies 3 cells of |
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read, write and setup latencies. Minimum valid values are 1. Controllers |
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without setup latency control should use a value of 0. |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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minItems: 2 |
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maxItems: 3 |
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items: |
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minimum: 0 |
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maximum: 8 |
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arm,tag-latency: |
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description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of |
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read, write and setup latencies. Controllers without setup latency control |
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should use 0. Controllers without separate read and write Tag RAM latency |
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values should only use the first cell. |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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minItems: 1 |
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maxItems: 3 |
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items: |
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minimum: 0 |
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maximum: 8 |
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arm,dirty-latency: |
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description: Cycles of latency for Dirty RAMs. This is a single cell. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 1 |
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maximum: 8 |
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arm,filter-ranges: |
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description: <start length> Starting address and length of window to |
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filter. Addresses in the filter window are directed to the M1 port. Other |
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addresses will go to the M0 port. |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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items: |
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minItems: 2 |
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maxItems: 2 |
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arm,io-coherent: |
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description: indicates that the system is operating in an hardware |
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I/O coherent mode. Valid only when the arm,pl310-cache compatible |
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string is used. |
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type: boolean |
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interrupts: |
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# Either a single combined interrupt or up to 9 individual interrupts |
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minItems: 1 |
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maxItems: 9 |
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cache-id-part: |
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description: cache id part number to be used if it is not present |
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on hardware |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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wt-override: |
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description: If present then L2 is forced to Write through mode |
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type: boolean |
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arm,double-linefill: |
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description: Override double linefill enable setting. Enable if |
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non-zero, disable if zero. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [0, 1] |
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arm,double-linefill-incr: |
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description: Override double linefill on INCR read. Enable |
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if non-zero, disable if zero. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [0, 1] |
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arm,double-linefill-wrap: |
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description: Override double linefill on WRAP read. Enable |
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if non-zero, disable if zero. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [0, 1] |
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arm,prefetch-drop: |
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description: Override prefetch drop enable setting. Enable if non-zero, |
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disable if zero. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [0, 1] |
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arm,prefetch-offset: |
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description: Override prefetch offset value. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31] |
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arm,shared-override: |
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description: The default behavior of the L220 or PL310 cache |
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controllers with respect to the shareable attribute is to transform "normal |
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memory non-cacheable transactions" into "cacheable no allocate" (for reads) |
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or "write through no write allocate" (for writes). |
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On systems where this may cause DMA buffer corruption, this property must |
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be specified to indicate that such transforms are precluded. |
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type: boolean |
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arm,parity-enable: |
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description: enable parity checking on the L2 cache (L220 or PL310). |
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type: boolean |
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arm,parity-disable: |
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description: disable parity checking on the L2 cache (L220 or PL310). |
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type: boolean |
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marvell,ecc-enable: |
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description: enable ECC protection on the L2 cache |
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type: boolean |
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arm,outer-sync-disable: |
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description: disable the outer sync operation on the L2 cache. |
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Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that |
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will randomly hang unless outer sync operations are disabled. |
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type: boolean |
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prefetch-data: |
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description: | |
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Data prefetch. Value: <0> (forcibly disable), <1> |
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(forcibly enable), property absent (retain settings set by firmware) |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [0, 1] |
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prefetch-instr: |
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description: | |
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Instruction prefetch. Value: <0> (forcibly disable), |
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<1> (forcibly enable), property absent (retain settings set by |
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firmware) |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [0, 1] |
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arm,dynamic-clock-gating: |
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description: | |
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L2 dynamic clock gating. Value: <0> (forcibly |
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disable), <1> (forcibly enable), property absent (OS specific behavior, |
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preferably retain firmware settings) |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [0, 1] |
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arm,standby-mode: |
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description: L2 standby mode enable. Value <0> (forcibly disable), |
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<1> (forcibly enable), property absent (OS specific behavior, |
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preferably retain firmware settings) |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [0, 1] |
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arm,early-bresp-disable: |
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description: Disable the CA9 optimization Early BRESP (PL310) |
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type: boolean |
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arm,full-line-zero-disable: |
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description: Disable the CA9 optimization Full line of zero |
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write (PL310) |
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type: boolean |
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required: |
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- compatible |
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- cache-unified |
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- reg |
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additionalProperties: false |
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examples: |
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- | |
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cache-controller@fff12000 { |
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compatible = "arm,pl310-cache"; |
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reg = <0xfff12000 0x1000>; |
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arm,data-latency = <1 1 1>; |
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arm,tag-latency = <2 2 2>; |
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arm,filter-ranges = <0x80000000 0x8000000>; |
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cache-unified; |
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cache-level = <2>; |
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interrupts = <45>; |
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}; |
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...
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