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45 lines
1.5 KiB
45 lines
1.5 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima |
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* Copyright (C) 2002 Paul Mundt |
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*/ |
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#ifndef __ASM_SH_BARRIER_H |
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#define __ASM_SH_BARRIER_H |
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#if defined(CONFIG_CPU_SH4A) |
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#include <asm/cache_insns.h> |
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#endif |
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/* |
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* A brief note on ctrl_barrier(), the control register write barrier. |
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* |
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* Legacy SH cores typically require a sequence of 8 nops after |
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* modification of a control register in order for the changes to take |
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* effect. On newer cores (like the sh4a and sh5) this is accomplished |
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* with icbi. |
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* |
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* Also note that on sh4a in the icbi case we can forego a synco for the |
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* write barrier, as it's not necessary for control registers. |
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* |
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* Historically we have only done this type of barrier for the MMUCR, but |
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* it's also necessary for the CCR, so we make it generic here instead. |
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*/ |
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#if defined(CONFIG_CPU_SH4A) |
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#define mb() __asm__ __volatile__ ("synco": : :"memory") |
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#define rmb() mb() |
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#define wmb() mb() |
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#define ctrl_barrier() __icbi(PAGE_OFFSET) |
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#else |
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#if defined(CONFIG_CPU_J2) && defined(CONFIG_SMP) |
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#define __smp_mb() do { int tmp = 0; __asm__ __volatile__ ("cas.l %0,%0,@%1" : "+r"(tmp) : "z"(&tmp) : "memory", "t"); } while(0) |
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#define __smp_rmb() __smp_mb() |
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#define __smp_wmb() __smp_mb() |
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#endif |
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#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") |
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#endif |
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#define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0) |
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#include <asm-generic/barrier.h> |
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#endif /* __ASM_SH_BARRIER_H */
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