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48 lines
1.3 KiB
48 lines
1.3 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __ASM_CSKY_PGTABLE_BITS_H |
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#define __ASM_CSKY_PGTABLE_BITS_H |
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/* implemented in software */ |
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#define _PAGE_ACCESSED (1<<7) |
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#define _PAGE_READ (1<<8) |
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#define _PAGE_WRITE (1<<9) |
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#define _PAGE_PRESENT (1<<10) |
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#define _PAGE_MODIFIED (1<<11) |
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/* implemented in hardware */ |
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#define _PAGE_GLOBAL (1<<0) |
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#define _PAGE_VALID (1<<1) |
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#define _PAGE_DIRTY (1<<2) |
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#define _PAGE_SO (1<<5) |
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#define _PAGE_BUF (1<<6) |
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#define _PAGE_CACHE (1<<3) |
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#define _CACHE_MASK _PAGE_CACHE |
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#define _CACHE_CACHED (_PAGE_CACHE | _PAGE_BUF) |
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#define _CACHE_UNCACHED (0) |
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#define _PAGE_PROT_NONE _PAGE_WRITE |
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/* |
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* Encode and decode a swap entry |
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* |
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* Format of swap PTE: |
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* bit 0: _PAGE_GLOBAL (zero) |
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* bit 1: _PAGE_VALID (zero) |
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* bit 2 - 6: swap type |
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* bit 7 - 8: swap offset[0 - 1] |
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* bit 9: _PAGE_WRITE (zero) |
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* bit 10: _PAGE_PRESENT (zero) |
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* bit 11 - 31: swap offset[2 - 22] |
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*/ |
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#define __swp_type(x) (((x).val >> 2) & 0x1f) |
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#define __swp_offset(x) ((((x).val >> 7) & 0x3) | \ |
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(((x).val >> 9) & 0x7ffffc)) |
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#define __swp_entry(type, offset) ((swp_entry_t) { \ |
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((type & 0x1f) << 2) | \ |
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((offset & 0x3) << 7) | \ |
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((offset & 0x7ffffc) << 9)}) |
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#endif /* __ASM_CSKY_PGTABLE_BITS_H */
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