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131 lines
2.9 KiB
131 lines
2.9 KiB
// SPDX-License-Identifier: GPL-2.0 |
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#include <linux/init.h> |
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#include <linux/list.h> |
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#include <linux/io.h> |
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#include <asm/mach/irq.h> |
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#include <asm/hardware/iomd.h> |
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#include <asm/irq.h> |
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#include <asm/fiq.h> |
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// These are offsets from the stat register for each IRQ bank |
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#define STAT 0x00 |
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#define REQ 0x04 |
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#define CLR 0x04 |
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#define MASK 0x08 |
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static void __iomem *iomd_get_base(struct irq_data *d) |
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{ |
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void *cd = irq_data_get_irq_chip_data(d); |
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return (void __iomem *)(unsigned long)cd; |
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} |
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static void iomd_set_base_mask(unsigned int irq, void __iomem *base, u32 mask) |
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{ |
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struct irq_data *d = irq_get_irq_data(irq); |
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d->mask = mask; |
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irq_set_chip_data(irq, (void *)(unsigned long)base); |
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} |
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static void iomd_irq_mask_ack(struct irq_data *d) |
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{ |
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void __iomem *base = iomd_get_base(d); |
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unsigned int val, mask = d->mask; |
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val = readb(base + MASK); |
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writeb(val & ~mask, base + MASK); |
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writeb(mask, base + CLR); |
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} |
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static void iomd_irq_mask(struct irq_data *d) |
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{ |
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void __iomem *base = iomd_get_base(d); |
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unsigned int val, mask = d->mask; |
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val = readb(base + MASK); |
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writeb(val & ~mask, base + MASK); |
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} |
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static void iomd_irq_unmask(struct irq_data *d) |
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{ |
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void __iomem *base = iomd_get_base(d); |
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unsigned int val, mask = d->mask; |
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val = readb(base + MASK); |
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writeb(val | mask, base + MASK); |
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} |
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static struct irq_chip iomd_chip_clr = { |
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.irq_mask_ack = iomd_irq_mask_ack, |
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.irq_mask = iomd_irq_mask, |
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.irq_unmask = iomd_irq_unmask, |
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}; |
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static struct irq_chip iomd_chip_noclr = { |
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.irq_mask = iomd_irq_mask, |
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.irq_unmask = iomd_irq_unmask, |
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}; |
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extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end; |
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void __init rpc_init_irq(void) |
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{ |
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unsigned int irq, clr, set; |
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iomd_writeb(0, IOMD_IRQMASKA); |
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iomd_writeb(0, IOMD_IRQMASKB); |
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iomd_writeb(0, IOMD_FIQMASK); |
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iomd_writeb(0, IOMD_DMAMASK); |
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set_fiq_handler(&rpc_default_fiq_start, |
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&rpc_default_fiq_end - &rpc_default_fiq_start); |
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for (irq = 0; irq < NR_IRQS; irq++) { |
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clr = IRQ_NOREQUEST; |
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set = 0; |
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if (irq <= 6 || (irq >= 9 && irq <= 15)) |
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clr |= IRQ_NOPROBE; |
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if (irq == 21 || (irq >= 16 && irq <= 19) || |
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irq == IRQ_KEYBOARDTX) |
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set |= IRQ_NOAUTOEN; |
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switch (irq) { |
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case 0 ... 7: |
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irq_set_chip_and_handler(irq, &iomd_chip_clr, |
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handle_level_irq); |
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irq_modify_status(irq, clr, set); |
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iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATA, |
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BIT(irq)); |
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break; |
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case 8 ... 15: |
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irq_set_chip_and_handler(irq, &iomd_chip_noclr, |
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handle_level_irq); |
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irq_modify_status(irq, clr, set); |
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iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATB, |
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BIT(irq - 8)); |
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break; |
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case 16 ... 21: |
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irq_set_chip_and_handler(irq, &iomd_chip_noclr, |
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handle_level_irq); |
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irq_modify_status(irq, clr, set); |
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iomd_set_base_mask(irq, IOMD_BASE + IOMD_DMASTAT, |
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BIT(irq - 16)); |
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break; |
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case 64 ... 71: |
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irq_set_chip(irq, &iomd_chip_noclr); |
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irq_modify_status(irq, clr, set); |
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iomd_set_base_mask(irq, IOMD_BASE + IOMD_FIQSTAT, |
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BIT(irq - 64)); |
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break; |
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} |
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} |
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init_FIQ(FIQ_START); |
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}
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