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589 lines
15 KiB
589 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* OMAP3 Power Management Routines |
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* |
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* Copyright (C) 2006-2008 Nokia Corporation |
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* Tony Lindgren <[email protected]> |
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* Jouni Hogander |
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* |
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* Copyright (C) 2007 Texas Instruments, Inc. |
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* Rajendra Nayak <[email protected]> |
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* |
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* Copyright (C) 2005 Texas Instruments, Inc. |
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* Richard Woodruff <[email protected]> |
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* |
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* Based on pm.c for omap1 |
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*/ |
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#include <linux/cpu_pm.h> |
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#include <linux/pm.h> |
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#include <linux/suspend.h> |
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include <linux/list.h> |
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#include <linux/err.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/slab.h> |
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#include <linux/of.h> |
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#include <linux/omap-gpmc.h> |
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#include <trace/events/power.h> |
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#include <asm/fncpy.h> |
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#include <asm/suspend.h> |
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#include <asm/system_misc.h> |
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#include "clockdomain.h" |
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#include "powerdomain.h" |
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#include "soc.h" |
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#include "common.h" |
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#include "cm3xxx.h" |
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#include "cm-regbits-34xx.h" |
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#include "prm-regbits-34xx.h" |
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#include "prm3xxx.h" |
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#include "pm.h" |
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#include "sdrc.h" |
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#include "omap-secure.h" |
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#include "sram.h" |
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#include "control.h" |
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#include "vc.h" |
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/* pm34xx errata defined in pm.h */ |
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u16 pm34xx_errata; |
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struct power_state { |
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struct powerdomain *pwrdm; |
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u32 next_state; |
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#ifdef CONFIG_SUSPEND |
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u32 saved_state; |
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#endif |
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struct list_head node; |
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}; |
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static LIST_HEAD(pwrst_list); |
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void (*omap3_do_wfi_sram)(void); |
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static struct powerdomain *mpu_pwrdm, *neon_pwrdm; |
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static struct powerdomain *core_pwrdm, *per_pwrdm; |
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static void omap3_core_save_context(void) |
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{ |
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omap3_ctrl_save_padconf(); |
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|
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/* |
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* Force write last pad into memory, as this can fail in some |
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* cases according to errata 1.157, 1.185 |
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*/ |
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omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), |
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OMAP343X_CONTROL_MEM_WKUP + 0x2a0); |
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/* Save the Interrupt controller context */ |
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omap_intc_save_context(); |
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/* Save the GPMC context */ |
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omap3_gpmc_save_context(); |
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/* Save the system control module context, padconf already save above*/ |
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omap3_control_save_context(); |
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} |
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static void omap3_core_restore_context(void) |
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{ |
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/* Restore the control module context, padconf restored by h/w */ |
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omap3_control_restore_context(); |
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/* Restore the GPMC context */ |
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omap3_gpmc_restore_context(); |
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/* Restore the interrupt controller context */ |
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omap_intc_restore_context(); |
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} |
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/* |
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* FIXME: This function should be called before entering off-mode after |
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* OMAP3 secure services have been accessed. Currently it is only called |
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* once during boot sequence, but this works as we are not using secure |
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* services. |
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*/ |
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static void omap3_save_secure_ram_context(void) |
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{ |
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u32 ret; |
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int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
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if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
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/* |
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* MPU next state must be set to POWER_ON temporarily, |
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* otherwise the WFI executed inside the ROM code |
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* will hang the system. |
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*/ |
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); |
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ret = omap3_save_secure_ram(omap3_secure_ram_storage, |
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OMAP3_SAVE_SECURE_RAM_SZ); |
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pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); |
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/* Following is for error tracking, it should not happen */ |
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if (ret) { |
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pr_err("save_secure_sram() returns %08x\n", ret); |
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while (1) |
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; |
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} |
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} |
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} |
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static irqreturn_t _prcm_int_handle_io(int irq, void *unused) |
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{ |
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int c; |
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c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK | |
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OMAP3430_ST_IO_CHAIN_MASK); |
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return c ? IRQ_HANDLED : IRQ_NONE; |
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} |
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static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) |
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{ |
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int c; |
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/* |
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* Clear all except ST_IO and ST_IO_CHAIN for wkup module, |
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* these are handled in a separate handler to avoid acking |
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* IO events before parsing in mux code |
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*/ |
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c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK | |
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OMAP3430_ST_IO_CHAIN_MASK)); |
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c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0); |
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c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0); |
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if (omap_rev() > OMAP3430_REV_ES1_0) { |
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c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0); |
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c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0); |
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} |
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return c ? IRQ_HANDLED : IRQ_NONE; |
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} |
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static void omap34xx_save_context(u32 *save) |
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{ |
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u32 val; |
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/* Read Auxiliary Control Register */ |
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asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); |
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*save++ = 1; |
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*save++ = val; |
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/* Read L2 AUX ctrl register */ |
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asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); |
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*save++ = 1; |
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*save++ = val; |
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} |
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static int omap34xx_do_sram_idle(unsigned long save_state) |
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{ |
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omap34xx_cpu_suspend(save_state); |
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return 0; |
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} |
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void omap_sram_idle(void) |
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{ |
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/* Variable to tell what needs to be saved and restored |
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* in omap_sram_idle*/ |
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/* save_state = 0 => Nothing to save and restored */ |
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/* save_state = 1 => Only L1 and logic lost */ |
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/* save_state = 2 => Only L2 lost */ |
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/* save_state = 3 => L1, L2 and logic lost */ |
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int save_state = 0; |
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int mpu_next_state = PWRDM_POWER_ON; |
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int per_next_state = PWRDM_POWER_ON; |
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int core_next_state = PWRDM_POWER_ON; |
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u32 sdrc_pwr = 0; |
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int error; |
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mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
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switch (mpu_next_state) { |
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case PWRDM_POWER_ON: |
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case PWRDM_POWER_RET: |
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/* No need to save context */ |
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save_state = 0; |
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break; |
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case PWRDM_POWER_OFF: |
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save_state = 3; |
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break; |
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default: |
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/* Invalid state */ |
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pr_err("Invalid mpu state in sram_idle\n"); |
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return; |
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} |
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/* NEON control */ |
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if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) |
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pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); |
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/* Enable IO-PAD and IO-CHAIN wakeups */ |
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per_next_state = pwrdm_read_next_pwrst(per_pwrdm); |
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core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
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pwrdm_pre_transition(NULL); |
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/* PER */ |
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if (per_next_state == PWRDM_POWER_OFF) { |
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error = cpu_cluster_pm_enter(); |
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if (error) |
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return; |
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} |
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/* CORE */ |
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if (core_next_state < PWRDM_POWER_ON) { |
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if (core_next_state == PWRDM_POWER_OFF) { |
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omap3_core_save_context(); |
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omap3_cm_save_context(); |
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} |
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} |
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/* Configure PMIC signaling for I2C4 or sys_off_mode */ |
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omap3_vc_set_pmic_signaling(core_next_state); |
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omap3_intc_prepare_idle(); |
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/* |
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* On EMU/HS devices ROM code restores a SRDC value |
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* from scratchpad which has automatic self refresh on timeout |
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* of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. |
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* Hence store/restore the SDRC_POWER register here. |
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*/ |
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if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && |
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(omap_type() == OMAP2_DEVICE_TYPE_EMU || |
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omap_type() == OMAP2_DEVICE_TYPE_SEC) && |
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core_next_state == PWRDM_POWER_OFF) |
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sdrc_pwr = sdrc_read_reg(SDRC_POWER); |
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/* |
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* omap3_arm_context is the location where some ARM context |
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* get saved. The rest is placed on the stack, and restored |
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* from there before resuming. |
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*/ |
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if (save_state) |
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omap34xx_save_context(omap3_arm_context); |
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if (save_state == 1 || save_state == 3) |
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cpu_suspend(save_state, omap34xx_do_sram_idle); |
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else |
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omap34xx_do_sram_idle(save_state); |
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/* Restore normal SDRC POWER settings */ |
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if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && |
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(omap_type() == OMAP2_DEVICE_TYPE_EMU || |
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omap_type() == OMAP2_DEVICE_TYPE_SEC) && |
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core_next_state == PWRDM_POWER_OFF) |
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sdrc_write_reg(sdrc_pwr, SDRC_POWER); |
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/* CORE */ |
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if (core_next_state < PWRDM_POWER_ON && |
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pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) { |
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omap3_core_restore_context(); |
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omap3_cm_restore_context(); |
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omap3_sram_restore_context(); |
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omap2_sms_restore_context(); |
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} else { |
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/* |
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* In off-mode resume path above, omap3_core_restore_context |
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* also handles the INTC autoidle restore done here so limit |
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* this to non-off mode resume paths so we don't do it twice. |
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*/ |
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omap3_intc_resume_idle(); |
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} |
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pwrdm_post_transition(NULL); |
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/* PER */ |
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if (per_next_state == PWRDM_POWER_OFF) |
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cpu_cluster_pm_exit(); |
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} |
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static void omap3_pm_idle(void) |
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{ |
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if (omap_irq_pending()) |
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return; |
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omap_sram_idle(); |
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} |
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#ifdef CONFIG_SUSPEND |
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static int omap3_pm_suspend(void) |
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{ |
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struct power_state *pwrst; |
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int state, ret = 0; |
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/* Read current next_pwrsts */ |
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list_for_each_entry(pwrst, &pwrst_list, node) |
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pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); |
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/* Set ones wanted by suspend */ |
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list_for_each_entry(pwrst, &pwrst_list, node) { |
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if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) |
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goto restore; |
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if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) |
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goto restore; |
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} |
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omap3_intc_suspend(); |
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omap_sram_idle(); |
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restore: |
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/* Restore next_pwrsts */ |
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list_for_each_entry(pwrst, &pwrst_list, node) { |
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state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
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if (state > pwrst->next_state) { |
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pr_info("Powerdomain (%s) didn't enter target state %d\n", |
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pwrst->pwrdm->name, pwrst->next_state); |
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ret = -1; |
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} |
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omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
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} |
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if (ret) |
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pr_err("Could not enter target state in pm_suspend\n"); |
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else |
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pr_info("Successfully put all powerdomains to target state\n"); |
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return ret; |
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} |
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#else |
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#define omap3_pm_suspend NULL |
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#endif /* CONFIG_SUSPEND */ |
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static void __init prcm_setup_regs(void) |
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{ |
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omap3_ctrl_init(); |
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omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva()); |
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} |
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void omap3_pm_off_mode_enable(int enable) |
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{ |
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struct power_state *pwrst; |
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u32 state; |
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if (enable) |
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state = PWRDM_POWER_OFF; |
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else |
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state = PWRDM_POWER_RET; |
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list_for_each_entry(pwrst, &pwrst_list, node) { |
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if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && |
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pwrst->pwrdm == core_pwrdm && |
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state == PWRDM_POWER_OFF) { |
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pwrst->next_state = PWRDM_POWER_RET; |
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pr_warn("%s: Core OFF disabled due to errata i583\n", |
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__func__); |
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} else { |
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pwrst->next_state = state; |
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} |
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omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
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} |
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} |
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int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) |
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{ |
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struct power_state *pwrst; |
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list_for_each_entry(pwrst, &pwrst_list, node) { |
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if (pwrst->pwrdm == pwrdm) |
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return pwrst->next_state; |
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} |
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return -EINVAL; |
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} |
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int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) |
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{ |
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struct power_state *pwrst; |
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list_for_each_entry(pwrst, &pwrst_list, node) { |
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if (pwrst->pwrdm == pwrdm) { |
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pwrst->next_state = state; |
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return 0; |
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} |
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} |
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return -EINVAL; |
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} |
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static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
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{ |
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struct power_state *pwrst; |
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if (!pwrdm->pwrsts) |
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return 0; |
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pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
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if (!pwrst) |
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return -ENOMEM; |
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pwrst->pwrdm = pwrdm; |
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if (enable_off_mode) |
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pwrst->next_state = PWRDM_POWER_OFF; |
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else |
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pwrst->next_state = PWRDM_POWER_RET; |
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list_add(&pwrst->node, &pwrst_list); |
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if (pwrdm_has_hdwr_sar(pwrdm)) |
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pwrdm_enable_hdwr_sar(pwrdm); |
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return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
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} |
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/* |
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* Push functions to SRAM |
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* |
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* The minimum set of functions is pushed to SRAM for execution: |
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* - omap3_do_wfi for erratum i581 WA, |
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*/ |
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void omap_push_sram_idle(void) |
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{ |
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omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); |
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} |
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static void __init pm_errata_configure(void) |
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{ |
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if (cpu_is_omap3630()) { |
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pm34xx_errata |= PM_RTA_ERRATUM_i608; |
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/* Enable the l2 cache toggling in sleep logic */ |
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enable_omap3630_toggle_l2_on_restore(); |
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if (omap_rev() < OMAP3630_REV_ES1_2) |
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pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 | |
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PM_PER_MEMORIES_ERRATUM_i582); |
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} else if (cpu_is_omap34xx()) { |
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pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582; |
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} |
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} |
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static void __init omap3_pm_check_pmic(void) |
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{ |
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struct device_node *np; |
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np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle"); |
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if (!np) |
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np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle-osc-off"); |
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if (np) { |
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of_node_put(np); |
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enable_off_mode = 1; |
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} else { |
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enable_off_mode = 0; |
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} |
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} |
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int __init omap3_pm_init(void) |
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{ |
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struct power_state *pwrst, *tmp; |
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struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm; |
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int ret; |
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if (!omap3_has_io_chain_ctrl()) |
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pr_warn("PM: no software I/O chain control; some wakeups may be lost\n"); |
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pm_errata_configure(); |
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/* XXX prcm_setup_regs needs to be before enabling hw |
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* supervised mode for powerdomains */ |
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prcm_setup_regs(); |
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ret = request_irq(omap_prcm_event_to_irq("wkup"), |
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_prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); |
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if (ret) { |
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pr_err("pm: Failed to request pm_wkup irq\n"); |
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goto err1; |
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} |
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/* IO interrupt is shared with mux code */ |
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ret = request_irq(omap_prcm_event_to_irq("io"), |
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_prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", |
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omap3_pm_init); |
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if (ret) { |
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pr_err("pm: Failed to request pm_io irq\n"); |
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goto err2; |
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} |
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omap3_pm_check_pmic(); |
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ret = pwrdm_for_each(pwrdms_setup, NULL); |
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if (ret) { |
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pr_err("Failed to setup powerdomains\n"); |
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goto err3; |
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} |
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(void) clkdm_for_each(omap_pm_clkdms_setup, NULL); |
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mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); |
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if (mpu_pwrdm == NULL) { |
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pr_err("Failed to get mpu_pwrdm\n"); |
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ret = -EINVAL; |
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goto err3; |
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} |
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neon_pwrdm = pwrdm_lookup("neon_pwrdm"); |
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per_pwrdm = pwrdm_lookup("per_pwrdm"); |
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core_pwrdm = pwrdm_lookup("core_pwrdm"); |
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neon_clkdm = clkdm_lookup("neon_clkdm"); |
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mpu_clkdm = clkdm_lookup("mpu_clkdm"); |
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per_clkdm = clkdm_lookup("per_clkdm"); |
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wkup_clkdm = clkdm_lookup("wkup_clkdm"); |
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omap_common_suspend_init(omap3_pm_suspend); |
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arm_pm_idle = omap3_pm_idle; |
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omap3_idle_init(); |
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|
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/* |
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* RTA is disabled during initialization as per erratum i608 |
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* it is safer to disable RTA by the bootloader, but we would like |
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* to be doubly sure here and prevent any mishaps. |
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*/ |
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if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) |
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omap3630_ctrl_disable_rta(); |
|
|
|
/* |
|
* The UART3/4 FIFO and the sidetone memory in McBSP2/3 are |
|
* not correctly reset when the PER powerdomain comes back |
|
* from OFF or OSWR when the CORE powerdomain is kept active. |
|
* See OMAP36xx Erratum i582 "PER Domain reset issue after |
|
* Domain-OFF/OSWR Wakeup". This wakeup dependency is not a |
|
* complete workaround. The kernel must also prevent the PER |
|
* powerdomain from going to OSWR/OFF while the CORE |
|
* powerdomain is not going to OSWR/OFF. And if PER last |
|
* power state was off while CORE last power state was ON, the |
|
* UART3/4 and McBSP2/3 SIDETONE devices need to run a |
|
* self-test using their loopback tests; if that fails, those |
|
* devices are unusable until the PER/CORE can complete a transition |
|
* from ON to OSWR/OFF and then back to ON. |
|
* |
|
* XXX Technically this workaround is only needed if off-mode |
|
* or OSWR is enabled. |
|
*/ |
|
if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582)) |
|
clkdm_add_wkdep(per_clkdm, wkup_clkdm); |
|
|
|
clkdm_add_wkdep(neon_clkdm, mpu_clkdm); |
|
if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
|
omap3_secure_ram_storage = |
|
kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL); |
|
if (!omap3_secure_ram_storage) |
|
pr_err("Memory allocation failed when allocating for secure sram context\n"); |
|
|
|
local_irq_disable(); |
|
|
|
omap3_save_secure_ram_context(); |
|
|
|
local_irq_enable(); |
|
} |
|
|
|
omap3_save_scratchpad_contents(); |
|
return ret; |
|
|
|
err3: |
|
list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { |
|
list_del(&pwrst->node); |
|
kfree(pwrst); |
|
} |
|
free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init); |
|
err2: |
|
free_irq(omap_prcm_event_to_irq("wkup"), NULL); |
|
err1: |
|
return ret; |
|
}
|
|
|