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279 lines
8.5 KiB
279 lines
8.5 KiB
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
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/* |
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* Header File for FPGA DFL User API |
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* |
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* Copyright (C) 2017-2018 Intel Corporation, Inc. |
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* |
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* Authors: |
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* Kang Luwei <[email protected]> |
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* Zhang Yi <[email protected]> |
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* Wu Hao <[email protected]> |
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* Xiao Guangrong <[email protected]> |
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*/ |
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#ifndef _UAPI_LINUX_FPGA_DFL_H |
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#define _UAPI_LINUX_FPGA_DFL_H |
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#include <linux/types.h> |
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#include <linux/ioctl.h> |
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#define DFL_FPGA_API_VERSION 0 |
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/* |
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* The IOCTL interface for DFL based FPGA is designed for extensibility by |
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* embedding the structure length (argsz) and flags into structures passed |
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* between kernel and userspace. This design referenced the VFIO IOCTL |
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* interface (include/uapi/linux/vfio.h). |
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*/ |
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#define DFL_FPGA_MAGIC 0xB6 |
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#define DFL_FPGA_BASE 0 |
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#define DFL_PORT_BASE 0x40 |
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#define DFL_FME_BASE 0x80 |
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/* Common IOCTLs for both FME and AFU file descriptor */ |
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/** |
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* DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) |
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* |
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* Report the version of the driver API. |
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* Return: Driver API Version. |
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*/ |
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#define DFL_FPGA_GET_API_VERSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) |
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/** |
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* DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) |
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* |
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* Check whether an extension is supported. |
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* Return: 0 if not supported, otherwise the extension is supported. |
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*/ |
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#define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) |
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/* IOCTLs for AFU file descriptor */ |
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/** |
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* DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0) |
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* |
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* Reset the FPGA Port and its AFU. No parameters are supported. |
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* Userspace can do Port reset at any time, e.g. during DMA or PR. But |
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* it should never cause any system level issue, only functional failure |
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* (e.g. DMA or PR operation failure) and be recoverable from the failure. |
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* Return: 0 on success, -errno of failure |
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*/ |
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#define DFL_FPGA_PORT_RESET _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0) |
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/** |
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* DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1, |
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* struct dfl_fpga_port_info) |
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* |
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* Retrieve information about the fpga port. |
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* Driver fills the info in provided struct dfl_fpga_port_info. |
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* Return: 0 on success, -errno on failure. |
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*/ |
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struct dfl_fpga_port_info { |
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/* Input */ |
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__u32 argsz; /* Structure length */ |
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/* Output */ |
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__u32 flags; /* Zero for now */ |
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__u32 num_regions; /* The number of supported regions */ |
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__u32 num_umsgs; /* The number of allocated umsgs */ |
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}; |
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#define DFL_FPGA_PORT_GET_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1) |
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/** |
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* FPGA_PORT_GET_REGION_INFO - _IOWR(FPGA_MAGIC, PORT_BASE + 2, |
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* struct dfl_fpga_port_region_info) |
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* |
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* Retrieve information about a device memory region. |
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* Caller provides struct dfl_fpga_port_region_info with index value set. |
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* Driver returns the region info in other fields. |
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* Return: 0 on success, -errno on failure. |
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*/ |
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struct dfl_fpga_port_region_info { |
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/* input */ |
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__u32 argsz; /* Structure length */ |
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/* Output */ |
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__u32 flags; /* Access permission */ |
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#define DFL_PORT_REGION_READ (1 << 0) /* Region is readable */ |
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#define DFL_PORT_REGION_WRITE (1 << 1) /* Region is writable */ |
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#define DFL_PORT_REGION_MMAP (1 << 2) /* Can be mmaped to userspace */ |
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/* Input */ |
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__u32 index; /* Region index */ |
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#define DFL_PORT_REGION_INDEX_AFU 0 /* AFU */ |
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#define DFL_PORT_REGION_INDEX_STP 1 /* Signal Tap */ |
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__u32 padding; |
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/* Output */ |
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__u64 size; /* Region size (bytes) */ |
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__u64 offset; /* Region offset from start of device fd */ |
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}; |
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#define DFL_FPGA_PORT_GET_REGION_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2) |
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/** |
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* DFL_FPGA_PORT_DMA_MAP - _IOWR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3, |
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* struct dfl_fpga_port_dma_map) |
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* |
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* Map the dma memory per user_addr and length which are provided by caller. |
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* Driver fills the iova in provided struct afu_port_dma_map. |
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* This interface only accepts page-size aligned user memory for dma mapping. |
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* Return: 0 on success, -errno on failure. |
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*/ |
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struct dfl_fpga_port_dma_map { |
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/* Input */ |
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__u32 argsz; /* Structure length */ |
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__u32 flags; /* Zero for now */ |
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__u64 user_addr; /* Process virtual address */ |
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__u64 length; /* Length of mapping (bytes)*/ |
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/* Output */ |
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__u64 iova; /* IO virtual address */ |
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}; |
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#define DFL_FPGA_PORT_DMA_MAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3) |
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/** |
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* DFL_FPGA_PORT_DMA_UNMAP - _IOW(FPGA_MAGIC, PORT_BASE + 4, |
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* struct dfl_fpga_port_dma_unmap) |
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* |
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* Unmap the dma memory per iova provided by caller. |
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* Return: 0 on success, -errno on failure. |
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*/ |
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struct dfl_fpga_port_dma_unmap { |
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/* Input */ |
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__u32 argsz; /* Structure length */ |
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__u32 flags; /* Zero for now */ |
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__u64 iova; /* IO virtual address */ |
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}; |
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#define DFL_FPGA_PORT_DMA_UNMAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 4) |
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/** |
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* struct dfl_fpga_irq_set - the argument for DFL_FPGA_XXX_SET_IRQ ioctl. |
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* |
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* @start: Index of the first irq. |
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* @count: The number of eventfd handler. |
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* @evtfds: Eventfd handlers. |
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*/ |
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struct dfl_fpga_irq_set { |
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__u32 start; |
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__u32 count; |
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__s32 evtfds[]; |
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}; |
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/** |
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* DFL_FPGA_PORT_ERR_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 5, |
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* __u32 num_irqs) |
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* |
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* Get the number of irqs supported by the fpga port error reporting private |
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* feature. Currently hardware supports up to 1 irq. |
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* Return: 0 on success, -errno on failure. |
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*/ |
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#define DFL_FPGA_PORT_ERR_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, \ |
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DFL_PORT_BASE + 5, __u32) |
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/** |
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* DFL_FPGA_PORT_ERR_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 6, |
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* struct dfl_fpga_irq_set) |
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* |
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* Set fpga port error reporting interrupt trigger if evtfds[n] is valid. |
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* Unset related interrupt trigger if evtfds[n] is a negative value. |
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* Return: 0 on success, -errno on failure. |
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*/ |
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#define DFL_FPGA_PORT_ERR_SET_IRQ _IOW(DFL_FPGA_MAGIC, \ |
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DFL_PORT_BASE + 6, \ |
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struct dfl_fpga_irq_set) |
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/** |
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* DFL_FPGA_PORT_UINT_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 7, |
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* __u32 num_irqs) |
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* |
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* Get the number of irqs supported by the fpga AFU interrupt private |
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* feature. |
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* Return: 0 on success, -errno on failure. |
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*/ |
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#define DFL_FPGA_PORT_UINT_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, \ |
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DFL_PORT_BASE + 7, __u32) |
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/** |
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* DFL_FPGA_PORT_UINT_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 8, |
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* struct dfl_fpga_irq_set) |
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* |
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* Set fpga AFU interrupt trigger if evtfds[n] is valid. |
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* Unset related interrupt trigger if evtfds[n] is a negative value. |
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* Return: 0 on success, -errno on failure. |
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*/ |
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#define DFL_FPGA_PORT_UINT_SET_IRQ _IOW(DFL_FPGA_MAGIC, \ |
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DFL_PORT_BASE + 8, \ |
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struct dfl_fpga_irq_set) |
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/* IOCTLs for FME file descriptor */ |
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/** |
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* DFL_FPGA_FME_PORT_PR - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 0, |
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* struct dfl_fpga_fme_port_pr) |
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* |
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* Driver does Partial Reconfiguration based on Port ID and Buffer (Image) |
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* provided by caller. |
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* Return: 0 on success, -errno on failure. |
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* If DFL_FPGA_FME_PORT_PR returns -EIO, that indicates the HW has detected |
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* some errors during PR, under this case, the user can fetch HW error info |
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* from the status of FME's fpga manager. |
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*/ |
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struct dfl_fpga_fme_port_pr { |
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/* Input */ |
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__u32 argsz; /* Structure length */ |
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__u32 flags; /* Zero for now */ |
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__u32 port_id; |
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__u32 buffer_size; |
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__u64 buffer_address; /* Userspace address to the buffer for PR */ |
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}; |
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#define DFL_FPGA_FME_PORT_PR _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0) |
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/** |
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* DFL_FPGA_FME_PORT_RELEASE - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1, |
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* int port_id) |
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* |
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* Driver releases the port per Port ID provided by caller. |
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* Return: 0 on success, -errno on failure. |
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*/ |
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#define DFL_FPGA_FME_PORT_RELEASE _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1, int) |
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/** |
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* DFL_FPGA_FME_PORT_ASSIGN - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2, |
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* int port_id) |
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* |
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* Driver assigns the port back per Port ID provided by caller. |
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* Return: 0 on success, -errno on failure. |
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*/ |
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#define DFL_FPGA_FME_PORT_ASSIGN _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2, int) |
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/** |
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* DFL_FPGA_FME_ERR_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_FME_BASE + 3, |
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* __u32 num_irqs) |
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* |
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* Get the number of irqs supported by the fpga fme error reporting private |
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* feature. Currently hardware supports up to 1 irq. |
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* Return: 0 on success, -errno on failure. |
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*/ |
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#define DFL_FPGA_FME_ERR_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, \ |
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DFL_FME_BASE + 3, __u32) |
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/** |
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* DFL_FPGA_FME_ERR_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 4, |
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* struct dfl_fpga_irq_set) |
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* |
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* Set fpga fme error reporting interrupt trigger if evtfds[n] is valid. |
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* Unset related interrupt trigger if evtfds[n] is a negative value. |
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* Return: 0 on success, -errno on failure. |
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*/ |
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#define DFL_FPGA_FME_ERR_SET_IRQ _IOW(DFL_FPGA_MAGIC, \ |
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DFL_FME_BASE + 4, \ |
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struct dfl_fpga_irq_set) |
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#endif /* _UAPI_LINUX_FPGA_DFL_H */
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