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362 lines
8.8 KiB
362 lines
8.8 KiB
/* |
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* drivers/char/watchdog/sp805-wdt.c |
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* |
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* Watchdog driver for ARM SP805 watchdog module |
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* |
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* Copyright (C) 2010 ST Microelectronics |
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* Viresh Kumar <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2 or later. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/device.h> |
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#include <linux/resource.h> |
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#include <linux/amba/bus.h> |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/ioport.h> |
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#include <linux/kernel.h> |
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#include <linux/math64.h> |
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#include <linux/module.h> |
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#include <linux/moduleparam.h> |
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#include <linux/pm.h> |
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#include <linux/property.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/types.h> |
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#include <linux/watchdog.h> |
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/* default timeout in seconds */ |
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#define DEFAULT_TIMEOUT 60 |
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#define MODULE_NAME "sp805-wdt" |
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/* watchdog register offsets and masks */ |
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#define WDTLOAD 0x000 |
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#define LOAD_MIN 0x00000001 |
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#define LOAD_MAX 0xFFFFFFFF |
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#define WDTVALUE 0x004 |
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#define WDTCONTROL 0x008 |
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/* control register masks */ |
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#define INT_ENABLE (1 << 0) |
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#define RESET_ENABLE (1 << 1) |
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#define ENABLE_MASK (INT_ENABLE | RESET_ENABLE) |
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#define WDTINTCLR 0x00C |
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#define WDTRIS 0x010 |
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#define WDTMIS 0x014 |
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#define INT_MASK (1 << 0) |
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#define WDTLOCK 0xC00 |
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#define UNLOCK 0x1ACCE551 |
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#define LOCK 0x00000001 |
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/** |
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* struct sp805_wdt: sp805 wdt device structure |
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* @wdd: instance of struct watchdog_device |
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* @lock: spin lock protecting dev structure and io access |
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* @base: base address of wdt |
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* @clk: (optional) clock structure of wdt |
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* @rate: (optional) clock rate when provided via properties |
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* @adev: amba device structure of wdt |
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* @status: current status of wdt |
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* @load_val: load value to be set for current timeout |
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*/ |
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struct sp805_wdt { |
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struct watchdog_device wdd; |
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spinlock_t lock; |
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void __iomem *base; |
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struct clk *clk; |
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u64 rate; |
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struct amba_device *adev; |
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unsigned int load_val; |
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}; |
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static bool nowayout = WATCHDOG_NOWAYOUT; |
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module_param(nowayout, bool, 0); |
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MODULE_PARM_DESC(nowayout, |
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"Set to 1 to keep watchdog running after device release"); |
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/* returns true if wdt is running; otherwise returns false */ |
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static bool wdt_is_running(struct watchdog_device *wdd) |
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{ |
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struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
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u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL); |
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return (wdtcontrol & ENABLE_MASK) == ENABLE_MASK; |
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} |
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/* This routine finds load value that will reset system in required timout */ |
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static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout) |
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{ |
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struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
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u64 load, rate; |
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rate = wdt->rate; |
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/* |
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* sp805 runs counter with given value twice, after the end of first |
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* counter it gives an interrupt and then starts counter again. If |
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* interrupt already occurred then it resets the system. This is why |
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* load is half of what should be required. |
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*/ |
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load = div_u64(rate, 2) * timeout - 1; |
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load = (load > LOAD_MAX) ? LOAD_MAX : load; |
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load = (load < LOAD_MIN) ? LOAD_MIN : load; |
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spin_lock(&wdt->lock); |
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wdt->load_val = load; |
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/* roundup timeout to closest positive integer value */ |
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wdd->timeout = div_u64((load + 1) * 2 + (rate / 2), rate); |
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spin_unlock(&wdt->lock); |
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return 0; |
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} |
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/* returns number of seconds left for reset to occur */ |
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static unsigned int wdt_timeleft(struct watchdog_device *wdd) |
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{ |
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struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
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u64 load; |
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spin_lock(&wdt->lock); |
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load = readl_relaxed(wdt->base + WDTVALUE); |
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/*If the interrupt is inactive then time left is WDTValue + WDTLoad. */ |
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if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK)) |
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load += wdt->load_val + 1; |
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spin_unlock(&wdt->lock); |
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return div_u64(load, wdt->rate); |
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} |
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static int |
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wdt_restart(struct watchdog_device *wdd, unsigned long mode, void *cmd) |
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{ |
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struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
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writel_relaxed(UNLOCK, wdt->base + WDTLOCK); |
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writel_relaxed(0, wdt->base + WDTCONTROL); |
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writel_relaxed(0, wdt->base + WDTLOAD); |
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writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL); |
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/* Flush posted writes. */ |
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readl_relaxed(wdt->base + WDTLOCK); |
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return 0; |
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} |
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static int wdt_config(struct watchdog_device *wdd, bool ping) |
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{ |
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struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
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int ret; |
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if (!ping) { |
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ret = clk_prepare_enable(wdt->clk); |
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if (ret) { |
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dev_err(&wdt->adev->dev, "clock enable fail"); |
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return ret; |
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} |
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} |
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spin_lock(&wdt->lock); |
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writel_relaxed(UNLOCK, wdt->base + WDTLOCK); |
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writel_relaxed(wdt->load_val, wdt->base + WDTLOAD); |
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writel_relaxed(INT_MASK, wdt->base + WDTINTCLR); |
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if (!ping) |
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writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + |
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WDTCONTROL); |
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writel_relaxed(LOCK, wdt->base + WDTLOCK); |
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/* Flush posted writes. */ |
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readl_relaxed(wdt->base + WDTLOCK); |
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spin_unlock(&wdt->lock); |
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return 0; |
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} |
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static int wdt_ping(struct watchdog_device *wdd) |
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{ |
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return wdt_config(wdd, true); |
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} |
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/* enables watchdog timers reset */ |
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static int wdt_enable(struct watchdog_device *wdd) |
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{ |
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return wdt_config(wdd, false); |
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} |
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/* disables watchdog timers reset */ |
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static int wdt_disable(struct watchdog_device *wdd) |
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{ |
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struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
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spin_lock(&wdt->lock); |
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writel_relaxed(UNLOCK, wdt->base + WDTLOCK); |
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writel_relaxed(0, wdt->base + WDTCONTROL); |
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writel_relaxed(LOCK, wdt->base + WDTLOCK); |
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/* Flush posted writes. */ |
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readl_relaxed(wdt->base + WDTLOCK); |
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spin_unlock(&wdt->lock); |
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clk_disable_unprepare(wdt->clk); |
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return 0; |
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} |
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static const struct watchdog_info wdt_info = { |
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.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, |
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.identity = MODULE_NAME, |
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}; |
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static const struct watchdog_ops wdt_ops = { |
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.owner = THIS_MODULE, |
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.start = wdt_enable, |
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.stop = wdt_disable, |
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.ping = wdt_ping, |
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.set_timeout = wdt_setload, |
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.get_timeleft = wdt_timeleft, |
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.restart = wdt_restart, |
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}; |
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static int |
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sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id) |
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{ |
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struct sp805_wdt *wdt; |
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u64 rate = 0; |
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int ret = 0; |
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wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL); |
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if (!wdt) { |
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ret = -ENOMEM; |
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goto err; |
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} |
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wdt->base = devm_ioremap_resource(&adev->dev, &adev->res); |
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if (IS_ERR(wdt->base)) |
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return PTR_ERR(wdt->base); |
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/* |
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* When driver probe with ACPI device, clock devices |
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* are not available, so watchdog rate get from |
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* clock-frequency property given in _DSD object. |
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*/ |
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device_property_read_u64(&adev->dev, "clock-frequency", &rate); |
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wdt->clk = devm_clk_get_optional(&adev->dev, NULL); |
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if (IS_ERR(wdt->clk)) |
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return dev_err_probe(&adev->dev, PTR_ERR(wdt->clk), "Clock not found\n"); |
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wdt->rate = clk_get_rate(wdt->clk); |
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if (!wdt->rate) |
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wdt->rate = rate; |
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if (!wdt->rate) { |
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dev_err(&adev->dev, "no clock-frequency property\n"); |
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return -ENODEV; |
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} |
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wdt->adev = adev; |
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wdt->wdd.info = &wdt_info; |
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wdt->wdd.ops = &wdt_ops; |
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wdt->wdd.parent = &adev->dev; |
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spin_lock_init(&wdt->lock); |
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watchdog_set_nowayout(&wdt->wdd, nowayout); |
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watchdog_set_drvdata(&wdt->wdd, wdt); |
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watchdog_set_restart_priority(&wdt->wdd, 128); |
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/* |
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* If 'timeout-sec' devicetree property is specified, use that. |
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* Otherwise, use DEFAULT_TIMEOUT |
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*/ |
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wdt->wdd.timeout = DEFAULT_TIMEOUT; |
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watchdog_init_timeout(&wdt->wdd, 0, &adev->dev); |
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wdt_setload(&wdt->wdd, wdt->wdd.timeout); |
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/* |
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* If HW is already running, enable/reset the wdt and set the running |
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* bit to tell the wdt subsystem |
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*/ |
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if (wdt_is_running(&wdt->wdd)) { |
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wdt_enable(&wdt->wdd); |
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set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); |
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} |
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watchdog_stop_on_reboot(&wdt->wdd); |
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ret = watchdog_register_device(&wdt->wdd); |
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if (ret) |
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goto err; |
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amba_set_drvdata(adev, wdt); |
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dev_info(&adev->dev, "registration successful\n"); |
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return 0; |
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err: |
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dev_err(&adev->dev, "Probe Failed!!!\n"); |
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return ret; |
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} |
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static void sp805_wdt_remove(struct amba_device *adev) |
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{ |
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struct sp805_wdt *wdt = amba_get_drvdata(adev); |
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watchdog_unregister_device(&wdt->wdd); |
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watchdog_set_drvdata(&wdt->wdd, NULL); |
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} |
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static int __maybe_unused sp805_wdt_suspend(struct device *dev) |
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{ |
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struct sp805_wdt *wdt = dev_get_drvdata(dev); |
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if (watchdog_active(&wdt->wdd)) |
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return wdt_disable(&wdt->wdd); |
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return 0; |
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} |
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static int __maybe_unused sp805_wdt_resume(struct device *dev) |
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{ |
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struct sp805_wdt *wdt = dev_get_drvdata(dev); |
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if (watchdog_active(&wdt->wdd)) |
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return wdt_enable(&wdt->wdd); |
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return 0; |
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} |
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static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend, |
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sp805_wdt_resume); |
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static const struct amba_id sp805_wdt_ids[] = { |
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{ |
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.id = 0x00141805, |
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.mask = 0x00ffffff, |
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}, |
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{ 0, 0 }, |
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}; |
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MODULE_DEVICE_TABLE(amba, sp805_wdt_ids); |
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static struct amba_driver sp805_wdt_driver = { |
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.drv = { |
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.name = MODULE_NAME, |
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.pm = &sp805_wdt_dev_pm_ops, |
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}, |
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.id_table = sp805_wdt_ids, |
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.probe = sp805_wdt_probe, |
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.remove = sp805_wdt_remove, |
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}; |
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module_amba_driver(sp805_wdt_driver); |
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MODULE_AUTHOR("Viresh Kumar <[email protected]>"); |
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MODULE_DESCRIPTION("ARM SP805 Watchdog Driver"); |
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MODULE_LICENSE("GPL");
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