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247 lines
6.0 KiB
247 lines
6.0 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Renesas RZ/A Series WDT Driver |
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* |
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* Copyright (C) 2017 Renesas Electronics America, Inc. |
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* Copyright (C) 2017 Chris Brandt |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/module.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/watchdog.h> |
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#define DEFAULT_TIMEOUT 30 |
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/* Watchdog Timer Registers */ |
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#define WTCSR 0 |
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#define WTCSR_MAGIC 0xA500 |
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#define WTSCR_WT BIT(6) |
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#define WTSCR_TME BIT(5) |
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#define WTSCR_CKS(i) (i) |
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#define WTCNT 2 |
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#define WTCNT_MAGIC 0x5A00 |
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#define WRCSR 4 |
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#define WRCSR_MAGIC 0x5A00 |
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#define WRCSR_RSTE BIT(6) |
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#define WRCSR_CLEAR_WOVF 0xA500 /* special value */ |
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/* The maximum CKS register setting value to get the longest timeout */ |
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#define CKS_3BIT 0x7 |
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#define CKS_4BIT 0xF |
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#define DIVIDER_3BIT 16384 /* Clock divider when CKS = 0x7 */ |
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#define DIVIDER_4BIT 4194304 /* Clock divider when CKS = 0xF */ |
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struct rza_wdt { |
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struct watchdog_device wdev; |
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void __iomem *base; |
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struct clk *clk; |
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u8 count; |
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u8 cks; |
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}; |
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static void rza_wdt_calc_timeout(struct rza_wdt *priv, int timeout) |
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{ |
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unsigned long rate = clk_get_rate(priv->clk); |
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unsigned int ticks; |
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if (priv->cks == CKS_4BIT) { |
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ticks = DIV_ROUND_UP(timeout * rate, DIVIDER_4BIT); |
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/* |
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* Since max_timeout was set in probe, we know that the timeout |
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* value passed will never calculate to a tick value greater |
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* than 256. |
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*/ |
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priv->count = 256 - ticks; |
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} else { |
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/* Start timer with longest timeout */ |
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priv->count = 0; |
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} |
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pr_debug("%s: timeout set to %u (WTCNT=%d)\n", __func__, |
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timeout, priv->count); |
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} |
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static int rza_wdt_start(struct watchdog_device *wdev) |
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{ |
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struct rza_wdt *priv = watchdog_get_drvdata(wdev); |
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/* Stop timer */ |
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writew(WTCSR_MAGIC | 0, priv->base + WTCSR); |
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/* Must dummy read WRCSR:WOVF at least once before clearing */ |
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readb(priv->base + WRCSR); |
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writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR); |
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rza_wdt_calc_timeout(priv, wdev->timeout); |
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writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR); |
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writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT); |
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writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME | |
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WTSCR_CKS(priv->cks), priv->base + WTCSR); |
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return 0; |
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} |
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static int rza_wdt_stop(struct watchdog_device *wdev) |
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{ |
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struct rza_wdt *priv = watchdog_get_drvdata(wdev); |
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writew(WTCSR_MAGIC | 0, priv->base + WTCSR); |
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return 0; |
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} |
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static int rza_wdt_ping(struct watchdog_device *wdev) |
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{ |
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struct rza_wdt *priv = watchdog_get_drvdata(wdev); |
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writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT); |
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pr_debug("%s: timeout = %u\n", __func__, wdev->timeout); |
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return 0; |
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} |
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static int rza_set_timeout(struct watchdog_device *wdev, unsigned int timeout) |
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{ |
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wdev->timeout = timeout; |
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rza_wdt_start(wdev); |
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return 0; |
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} |
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static int rza_wdt_restart(struct watchdog_device *wdev, unsigned long action, |
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void *data) |
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{ |
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struct rza_wdt *priv = watchdog_get_drvdata(wdev); |
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/* Stop timer */ |
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writew(WTCSR_MAGIC | 0, priv->base + WTCSR); |
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/* Must dummy read WRCSR:WOVF at least once before clearing */ |
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readb(priv->base + WRCSR); |
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writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR); |
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/* |
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* Start timer with fastest clock source and only 1 clock left before |
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* overflow with reset option enabled. |
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*/ |
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writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR); |
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writew(WTCNT_MAGIC | 255, priv->base + WTCNT); |
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writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME, priv->base + WTCSR); |
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/* |
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* Actually make sure the above sequence hits hardware before sleeping. |
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*/ |
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wmb(); |
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/* Wait for WDT overflow (reset) */ |
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udelay(20); |
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return 0; |
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} |
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static const struct watchdog_info rza_wdt_ident = { |
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.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, |
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.identity = "Renesas RZ/A WDT Watchdog", |
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}; |
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static const struct watchdog_ops rza_wdt_ops = { |
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.owner = THIS_MODULE, |
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.start = rza_wdt_start, |
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.stop = rza_wdt_stop, |
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.ping = rza_wdt_ping, |
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.set_timeout = rza_set_timeout, |
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.restart = rza_wdt_restart, |
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}; |
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static int rza_wdt_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct rza_wdt *priv; |
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unsigned long rate; |
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int ret; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(priv->base)) |
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return PTR_ERR(priv->base); |
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priv->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(priv->clk)) |
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return PTR_ERR(priv->clk); |
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rate = clk_get_rate(priv->clk); |
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if (rate < 16384) { |
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dev_err(dev, "invalid clock rate (%ld)\n", rate); |
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return -ENOENT; |
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} |
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priv->wdev.info = &rza_wdt_ident, |
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priv->wdev.ops = &rza_wdt_ops, |
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priv->wdev.parent = dev; |
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priv->cks = (u8)(uintptr_t) of_device_get_match_data(dev); |
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if (priv->cks == CKS_4BIT) { |
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/* Assume slowest clock rate possible (CKS=0xF) */ |
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priv->wdev.max_timeout = (DIVIDER_4BIT * U8_MAX) / rate; |
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} else if (priv->cks == CKS_3BIT) { |
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/* Assume slowest clock rate possible (CKS=7) */ |
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rate /= DIVIDER_3BIT; |
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/* |
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* Since the max possible timeout of our 8-bit count |
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* register is less than a second, we must use |
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* max_hw_heartbeat_ms. |
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*/ |
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priv->wdev.max_hw_heartbeat_ms = (1000 * U8_MAX) / rate; |
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dev_dbg(dev, "max hw timeout of %dms\n", |
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priv->wdev.max_hw_heartbeat_ms); |
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} |
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priv->wdev.min_timeout = 1; |
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priv->wdev.timeout = DEFAULT_TIMEOUT; |
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watchdog_init_timeout(&priv->wdev, 0, dev); |
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watchdog_set_drvdata(&priv->wdev, priv); |
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ret = devm_watchdog_register_device(dev, &priv->wdev); |
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if (ret) |
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dev_err(dev, "Cannot register watchdog device\n"); |
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return ret; |
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} |
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static const struct of_device_id rza_wdt_of_match[] = { |
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{ .compatible = "renesas,r7s9210-wdt", .data = (void *)CKS_4BIT, }, |
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{ .compatible = "renesas,rza-wdt", .data = (void *)CKS_3BIT, }, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, rza_wdt_of_match); |
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static struct platform_driver rza_wdt_driver = { |
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.probe = rza_wdt_probe, |
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.driver = { |
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.name = "rza_wdt", |
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.of_match_table = rza_wdt_of_match, |
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}, |
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}; |
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module_platform_driver(rza_wdt_driver); |
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MODULE_DESCRIPTION("Renesas RZ/A WDT Driver"); |
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MODULE_AUTHOR("Chris Brandt <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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