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664 lines
18 KiB
664 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* intel TCO Watchdog Driver |
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* |
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* (c) Copyright 2006-2011 Wim Van Sebroeck <[email protected]>. |
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* |
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* Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor |
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* provide warranty for any of this software. This material is |
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* provided "AS-IS" and at no charge. |
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* |
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* The TCO watchdog is implemented in the following I/O controller hubs: |
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* (See the intel documentation on http://developer.intel.com.) |
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* document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) |
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* document number 290687-002, 298242-027: 82801BA (ICH2) |
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* document number 290733-003, 290739-013: 82801CA (ICH3-S) |
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* document number 290716-001, 290718-007: 82801CAM (ICH3-M) |
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* document number 290744-001, 290745-025: 82801DB (ICH4) |
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* document number 252337-001, 252663-008: 82801DBM (ICH4-M) |
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* document number 273599-001, 273645-002: 82801E (C-ICH) |
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* document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) |
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* document number 300641-004, 300884-013: 6300ESB |
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* document number 301473-002, 301474-026: 82801F (ICH6) |
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* document number 313082-001, 313075-006: 631xESB, 632xESB |
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* document number 307013-003, 307014-024: 82801G (ICH7) |
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* document number 322896-001, 322897-001: NM10 |
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* document number 313056-003, 313057-017: 82801H (ICH8) |
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* document number 316972-004, 316973-012: 82801I (ICH9) |
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* document number 319973-002, 319974-002: 82801J (ICH10) |
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* document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) |
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* document number 320066-003, 320257-008: EP80597 (IICH) |
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* document number 324645-001, 324646-001: Cougar Point (CPT) |
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* document number TBD : Patsburg (PBG) |
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* document number TBD : DH89xxCC |
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* document number TBD : Panther Point |
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* document number TBD : Lynx Point |
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* document number TBD : Lynx Point-LP |
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*/ |
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|
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/* |
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* Includes, defines, variables, module parameters, ... |
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*/ |
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|
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/* Module and version information */ |
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#define DRV_NAME "iTCO_wdt" |
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#define DRV_VERSION "1.11" |
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|
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/* Includes */ |
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#include <linux/acpi.h> /* For ACPI support */ |
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#include <linux/bits.h> /* For BIT() */ |
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#include <linux/module.h> /* For module specific items */ |
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#include <linux/moduleparam.h> /* For new moduleparam's */ |
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#include <linux/types.h> /* For standard types (like size_t) */ |
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#include <linux/errno.h> /* For the -ENODEV/... values */ |
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#include <linux/kernel.h> /* For printk/panic/... */ |
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#include <linux/watchdog.h> /* For the watchdog specific items */ |
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#include <linux/init.h> /* For __init/__exit/... */ |
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#include <linux/fs.h> /* For file operations */ |
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#include <linux/platform_device.h> /* For platform_driver framework */ |
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#include <linux/pci.h> /* For pci functions */ |
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#include <linux/ioport.h> /* For io-port access */ |
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#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ |
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#include <linux/uaccess.h> /* For copy_to_user/put_user/... */ |
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#include <linux/io.h> /* For inb/outb/... */ |
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#include <linux/platform_data/itco_wdt.h> |
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#include <linux/mfd/intel_pmc_bxt.h> |
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|
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#include "iTCO_vendor.h" |
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|
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/* Address definitions for the TCO */ |
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/* TCO base address */ |
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#define TCOBASE(p) ((p)->tco_res->start) |
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/* SMI Control and Enable Register */ |
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#define SMI_EN(p) ((p)->smi_res->start) |
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#define TCO_EN (1 << 13) |
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#define GBL_SMI_EN (1 << 0) |
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|
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#define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */ |
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#define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/ |
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#define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */ |
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#define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */ |
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#define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */ |
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#define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */ |
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#define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */ |
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#define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */ |
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#define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/ |
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|
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/* internal variables */ |
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struct iTCO_wdt_private { |
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struct watchdog_device wddev; |
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|
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/* TCO version/generation */ |
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unsigned int iTCO_version; |
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struct resource *tco_res; |
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struct resource *smi_res; |
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/* |
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* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2), |
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* or memory-mapped PMC register bit 4 (TCO version 3). |
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*/ |
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struct resource *gcs_pmc_res; |
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unsigned long __iomem *gcs_pmc; |
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/* the lock for io operations */ |
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spinlock_t io_lock; |
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/* the PCI-device */ |
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struct pci_dev *pci_dev; |
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/* whether or not the watchdog has been suspended */ |
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bool suspended; |
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/* no reboot API private data */ |
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void *no_reboot_priv; |
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/* no reboot update function pointer */ |
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int (*update_no_reboot_bit)(void *p, bool set); |
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}; |
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|
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/* module parameters */ |
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#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */ |
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static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */ |
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module_param(heartbeat, int, 0); |
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MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. " |
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"5..76 (TCO v1) or 3..614 (TCO v2), default=" |
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__MODULE_STRING(WATCHDOG_TIMEOUT) ")"); |
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|
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static bool nowayout = WATCHDOG_NOWAYOUT; |
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module_param(nowayout, bool, 0); |
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MODULE_PARM_DESC(nowayout, |
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"Watchdog cannot be stopped once started (default=" |
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
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|
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static int turn_SMI_watchdog_clear_off = 1; |
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module_param(turn_SMI_watchdog_clear_off, int, 0); |
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MODULE_PARM_DESC(turn_SMI_watchdog_clear_off, |
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"Turn off SMI clearing watchdog (depends on TCO-version)(default=1)"); |
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|
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/* |
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* Some TCO specific functions |
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*/ |
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|
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/* |
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* The iTCO v1 and v2's internal timer is stored as ticks which decrement |
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* every 0.6 seconds. v3's internal timer is stored as seconds (some |
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* datasheets incorrectly state 0.6 seconds). |
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*/ |
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static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p, |
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int secs) |
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{ |
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return p->iTCO_version == 3 ? secs : (secs * 10) / 6; |
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} |
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|
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static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p, |
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int ticks) |
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{ |
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return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10; |
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} |
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|
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static inline u32 no_reboot_bit(struct iTCO_wdt_private *p) |
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{ |
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u32 enable_bit; |
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|
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switch (p->iTCO_version) { |
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case 5: |
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case 3: |
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enable_bit = 0x00000010; |
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break; |
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case 2: |
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enable_bit = 0x00000020; |
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break; |
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case 4: |
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case 1: |
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default: |
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enable_bit = 0x00000002; |
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break; |
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} |
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return enable_bit; |
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} |
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|
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static int update_no_reboot_bit_def(void *priv, bool set) |
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{ |
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return 0; |
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} |
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|
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static int update_no_reboot_bit_pci(void *priv, bool set) |
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{ |
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struct iTCO_wdt_private *p = priv; |
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u32 val32 = 0, newval32 = 0; |
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|
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pci_read_config_dword(p->pci_dev, 0xd4, &val32); |
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if (set) |
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val32 |= no_reboot_bit(p); |
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else |
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val32 &= ~no_reboot_bit(p); |
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pci_write_config_dword(p->pci_dev, 0xd4, val32); |
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pci_read_config_dword(p->pci_dev, 0xd4, &newval32); |
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|
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/* make sure the update is successful */ |
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if (val32 != newval32) |
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return -EIO; |
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|
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return 0; |
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} |
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|
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static int update_no_reboot_bit_mem(void *priv, bool set) |
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{ |
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struct iTCO_wdt_private *p = priv; |
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u32 val32 = 0, newval32 = 0; |
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|
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val32 = readl(p->gcs_pmc); |
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if (set) |
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val32 |= no_reboot_bit(p); |
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else |
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val32 &= ~no_reboot_bit(p); |
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writel(val32, p->gcs_pmc); |
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newval32 = readl(p->gcs_pmc); |
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|
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/* make sure the update is successful */ |
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if (val32 != newval32) |
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return -EIO; |
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return 0; |
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} |
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static int update_no_reboot_bit_cnt(void *priv, bool set) |
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{ |
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struct iTCO_wdt_private *p = priv; |
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u16 val, newval; |
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val = inw(TCO1_CNT(p)); |
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if (set) |
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val |= BIT(0); |
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else |
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val &= ~BIT(0); |
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outw(val, TCO1_CNT(p)); |
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newval = inw(TCO1_CNT(p)); |
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|
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/* make sure the update is successful */ |
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return val != newval ? -EIO : 0; |
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} |
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|
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static int update_no_reboot_bit_pmc(void *priv, bool set) |
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{ |
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struct intel_pmc_dev *pmc = priv; |
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u32 bits = PMC_CFG_NO_REBOOT_EN; |
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u32 value = set ? bits : 0; |
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|
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return intel_pmc_gcr_update(pmc, PMC_GCR_PMC_CFG_REG, bits, value); |
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} |
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static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p, |
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struct platform_device *pdev, |
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struct itco_wdt_platform_data *pdata) |
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{ |
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if (pdata->no_reboot_use_pmc) { |
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struct intel_pmc_dev *pmc = dev_get_drvdata(pdev->dev.parent); |
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p->update_no_reboot_bit = update_no_reboot_bit_pmc; |
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p->no_reboot_priv = pmc; |
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return; |
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} |
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if (p->iTCO_version >= 6) |
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p->update_no_reboot_bit = update_no_reboot_bit_cnt; |
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else if (p->iTCO_version >= 2) |
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p->update_no_reboot_bit = update_no_reboot_bit_mem; |
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else if (p->iTCO_version == 1) |
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p->update_no_reboot_bit = update_no_reboot_bit_pci; |
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else |
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p->update_no_reboot_bit = update_no_reboot_bit_def; |
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p->no_reboot_priv = p; |
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} |
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static int iTCO_wdt_start(struct watchdog_device *wd_dev) |
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{ |
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struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
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unsigned int val; |
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spin_lock(&p->io_lock); |
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iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout); |
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/* disable chipset's NO_REBOOT bit */ |
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if (p->update_no_reboot_bit(p->no_reboot_priv, false)) { |
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spin_unlock(&p->io_lock); |
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dev_err(wd_dev->parent, "failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n"); |
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return -EIO; |
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} |
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/* Force the timer to its reload value by writing to the TCO_RLD |
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register */ |
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if (p->iTCO_version >= 2) |
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outw(0x01, TCO_RLD(p)); |
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else if (p->iTCO_version == 1) |
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outb(0x01, TCO_RLD(p)); |
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|
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/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */ |
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val = inw(TCO1_CNT(p)); |
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val &= 0xf7ff; |
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outw(val, TCO1_CNT(p)); |
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val = inw(TCO1_CNT(p)); |
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spin_unlock(&p->io_lock); |
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|
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if (val & 0x0800) |
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return -1; |
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return 0; |
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} |
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static int iTCO_wdt_stop(struct watchdog_device *wd_dev) |
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{ |
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struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
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unsigned int val; |
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|
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spin_lock(&p->io_lock); |
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iTCO_vendor_pre_stop(p->smi_res); |
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|
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/* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */ |
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val = inw(TCO1_CNT(p)); |
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val |= 0x0800; |
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outw(val, TCO1_CNT(p)); |
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val = inw(TCO1_CNT(p)); |
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|
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/* Set the NO_REBOOT bit to prevent later reboots, just for sure */ |
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p->update_no_reboot_bit(p->no_reboot_priv, true); |
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spin_unlock(&p->io_lock); |
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if ((val & 0x0800) == 0) |
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return -1; |
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return 0; |
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} |
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static int iTCO_wdt_ping(struct watchdog_device *wd_dev) |
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{ |
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struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
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|
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spin_lock(&p->io_lock); |
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|
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/* Reload the timer by writing to the TCO Timer Counter register */ |
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if (p->iTCO_version >= 2) { |
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outw(0x01, TCO_RLD(p)); |
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} else if (p->iTCO_version == 1) { |
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/* Reset the timeout status bit so that the timer |
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* needs to count down twice again before rebooting */ |
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outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */ |
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|
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outb(0x01, TCO_RLD(p)); |
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} |
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|
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spin_unlock(&p->io_lock); |
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return 0; |
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} |
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|
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static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t) |
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{ |
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struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
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unsigned int val16; |
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unsigned char val8; |
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unsigned int tmrval; |
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|
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tmrval = seconds_to_ticks(p, t); |
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|
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/* |
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* If TCO SMIs are off, the timer counts down twice before rebooting. |
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* Otherwise, the BIOS generally reboots when the SMI triggers. |
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*/ |
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if (p->smi_res && |
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(inl(SMI_EN(p)) & (TCO_EN | GBL_SMI_EN)) != (TCO_EN | GBL_SMI_EN)) |
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tmrval /= 2; |
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|
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/* from the specs: */ |
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/* "Values of 0h-3h are ignored and should not be attempted" */ |
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if (tmrval < 0x04) |
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return -EINVAL; |
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if ((p->iTCO_version >= 2 && tmrval > 0x3ff) || |
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(p->iTCO_version == 1 && tmrval > 0x03f)) |
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return -EINVAL; |
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|
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/* Write new heartbeat to watchdog */ |
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if (p->iTCO_version >= 2) { |
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spin_lock(&p->io_lock); |
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val16 = inw(TCOv2_TMR(p)); |
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val16 &= 0xfc00; |
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val16 |= tmrval; |
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outw(val16, TCOv2_TMR(p)); |
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val16 = inw(TCOv2_TMR(p)); |
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spin_unlock(&p->io_lock); |
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|
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if ((val16 & 0x3ff) != tmrval) |
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return -EINVAL; |
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} else if (p->iTCO_version == 1) { |
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spin_lock(&p->io_lock); |
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val8 = inb(TCOv1_TMR(p)); |
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val8 &= 0xc0; |
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val8 |= (tmrval & 0xff); |
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outb(val8, TCOv1_TMR(p)); |
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val8 = inb(TCOv1_TMR(p)); |
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spin_unlock(&p->io_lock); |
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|
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if ((val8 & 0x3f) != tmrval) |
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return -EINVAL; |
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} |
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|
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wd_dev->timeout = t; |
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return 0; |
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} |
|
|
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static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev) |
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{ |
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struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev); |
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unsigned int val16; |
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unsigned char val8; |
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unsigned int time_left = 0; |
|
|
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/* read the TCO Timer */ |
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if (p->iTCO_version >= 2) { |
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spin_lock(&p->io_lock); |
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val16 = inw(TCO_RLD(p)); |
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val16 &= 0x3ff; |
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spin_unlock(&p->io_lock); |
|
|
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time_left = ticks_to_seconds(p, val16); |
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} else if (p->iTCO_version == 1) { |
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spin_lock(&p->io_lock); |
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val8 = inb(TCO_RLD(p)); |
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val8 &= 0x3f; |
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if (!(inw(TCO1_STS(p)) & 0x0008)) |
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val8 += (inb(TCOv1_TMR(p)) & 0x3f); |
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spin_unlock(&p->io_lock); |
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|
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time_left = ticks_to_seconds(p, val8); |
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} |
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return time_left; |
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} |
|
|
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/* |
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* Kernel Interfaces |
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*/ |
|
|
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static const struct watchdog_info ident = { |
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.options = WDIOF_SETTIMEOUT | |
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WDIOF_KEEPALIVEPING | |
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WDIOF_MAGICCLOSE, |
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.firmware_version = 0, |
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.identity = DRV_NAME, |
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}; |
|
|
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static const struct watchdog_ops iTCO_wdt_ops = { |
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.owner = THIS_MODULE, |
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.start = iTCO_wdt_start, |
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.stop = iTCO_wdt_stop, |
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.ping = iTCO_wdt_ping, |
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.set_timeout = iTCO_wdt_set_timeout, |
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.get_timeleft = iTCO_wdt_get_timeleft, |
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}; |
|
|
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/* |
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* Init & exit routines |
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*/ |
|
|
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static int iTCO_wdt_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct itco_wdt_platform_data *pdata = dev_get_platdata(dev); |
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struct iTCO_wdt_private *p; |
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unsigned long val32; |
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int ret; |
|
|
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if (!pdata) |
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return -ENODEV; |
|
|
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p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); |
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if (!p) |
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return -ENOMEM; |
|
|
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spin_lock_init(&p->io_lock); |
|
|
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p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO); |
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if (!p->tco_res) |
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return -ENODEV; |
|
|
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p->iTCO_version = pdata->version; |
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p->pci_dev = to_pci_dev(dev->parent); |
|
|
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p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI); |
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if (p->smi_res) { |
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/* The TCO logic uses the TCO_EN bit in the SMI_EN register */ |
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if (!devm_request_region(dev, p->smi_res->start, |
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resource_size(p->smi_res), |
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pdev->name)) { |
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dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n", |
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(u64)SMI_EN(p)); |
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return -EBUSY; |
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} |
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} else if (iTCO_vendorsupport || |
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turn_SMI_watchdog_clear_off >= p->iTCO_version) { |
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dev_err(dev, "SMI I/O resource is missing\n"); |
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return -ENODEV; |
|
} |
|
|
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iTCO_wdt_no_reboot_bit_setup(p, pdev, pdata); |
|
|
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/* |
|
* Get the Memory-Mapped GCS or PMC register, we need it for the |
|
* NO_REBOOT flag (TCO v2 and v3). |
|
*/ |
|
if (p->iTCO_version >= 2 && p->iTCO_version < 6 && |
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!pdata->no_reboot_use_pmc) { |
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p->gcs_pmc_res = platform_get_resource(pdev, |
|
IORESOURCE_MEM, |
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ICH_RES_MEM_GCS_PMC); |
|
p->gcs_pmc = devm_ioremap_resource(dev, p->gcs_pmc_res); |
|
if (IS_ERR(p->gcs_pmc)) |
|
return PTR_ERR(p->gcs_pmc); |
|
} |
|
|
|
/* Check chipset's NO_REBOOT bit */ |
|
if (p->update_no_reboot_bit(p->no_reboot_priv, false) && |
|
iTCO_vendor_check_noreboot_on()) { |
|
dev_info(dev, "unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n"); |
|
return -ENODEV; /* Cannot reset NO_REBOOT bit */ |
|
} |
|
|
|
/* Set the NO_REBOOT bit to prevent later reboots, just for sure */ |
|
p->update_no_reboot_bit(p->no_reboot_priv, true); |
|
|
|
if (turn_SMI_watchdog_clear_off >= p->iTCO_version) { |
|
/* |
|
* Bit 13: TCO_EN -> 0 |
|
* Disables TCO logic generating an SMI# |
|
*/ |
|
val32 = inl(SMI_EN(p)); |
|
val32 &= ~TCO_EN; /* Turn off SMI clearing watchdog */ |
|
outl(val32, SMI_EN(p)); |
|
} |
|
|
|
if (!devm_request_region(dev, p->tco_res->start, |
|
resource_size(p->tco_res), |
|
pdev->name)) { |
|
dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n", |
|
(u64)TCOBASE(p)); |
|
return -EBUSY; |
|
} |
|
|
|
dev_info(dev, "Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n", |
|
pdata->name, pdata->version, (u64)TCOBASE(p)); |
|
|
|
/* Clear out the (probably old) status */ |
|
switch (p->iTCO_version) { |
|
case 6: |
|
case 5: |
|
case 4: |
|
outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */ |
|
outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */ |
|
break; |
|
case 3: |
|
outl(0x20008, TCO1_STS(p)); |
|
break; |
|
case 2: |
|
case 1: |
|
default: |
|
outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */ |
|
outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */ |
|
outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */ |
|
break; |
|
} |
|
|
|
p->wddev.info = &ident, |
|
p->wddev.ops = &iTCO_wdt_ops, |
|
p->wddev.bootstatus = 0; |
|
p->wddev.timeout = WATCHDOG_TIMEOUT; |
|
watchdog_set_nowayout(&p->wddev, nowayout); |
|
p->wddev.parent = dev; |
|
|
|
watchdog_set_drvdata(&p->wddev, p); |
|
platform_set_drvdata(pdev, p); |
|
|
|
/* Make sure the watchdog is not running */ |
|
iTCO_wdt_stop(&p->wddev); |
|
|
|
/* Check that the heartbeat value is within it's range; |
|
if not reset to the default */ |
|
if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) { |
|
iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT); |
|
dev_info(dev, "timeout value out of range, using %d\n", |
|
WATCHDOG_TIMEOUT); |
|
} |
|
|
|
watchdog_stop_on_reboot(&p->wddev); |
|
watchdog_stop_on_unregister(&p->wddev); |
|
ret = devm_watchdog_register_device(dev, &p->wddev); |
|
if (ret != 0) { |
|
dev_err(dev, "cannot register watchdog device (err=%d)\n", ret); |
|
return ret; |
|
} |
|
|
|
dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n", |
|
heartbeat, nowayout); |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
/* |
|
* Suspend-to-idle requires this, because it stops the ticks and timekeeping, so |
|
* the watchdog cannot be pinged while in that state. In ACPI sleep states the |
|
* watchdog is stopped by the platform firmware. |
|
*/ |
|
|
|
#ifdef CONFIG_ACPI |
|
static inline bool need_suspend(void) |
|
{ |
|
return acpi_target_system_state() == ACPI_STATE_S0; |
|
} |
|
#else |
|
static inline bool need_suspend(void) { return true; } |
|
#endif |
|
|
|
static int iTCO_wdt_suspend_noirq(struct device *dev) |
|
{ |
|
struct iTCO_wdt_private *p = dev_get_drvdata(dev); |
|
int ret = 0; |
|
|
|
p->suspended = false; |
|
if (watchdog_active(&p->wddev) && need_suspend()) { |
|
ret = iTCO_wdt_stop(&p->wddev); |
|
if (!ret) |
|
p->suspended = true; |
|
} |
|
return ret; |
|
} |
|
|
|
static int iTCO_wdt_resume_noirq(struct device *dev) |
|
{ |
|
struct iTCO_wdt_private *p = dev_get_drvdata(dev); |
|
|
|
if (p->suspended) |
|
iTCO_wdt_start(&p->wddev); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops iTCO_wdt_pm = { |
|
.suspend_noirq = iTCO_wdt_suspend_noirq, |
|
.resume_noirq = iTCO_wdt_resume_noirq, |
|
}; |
|
|
|
#define ITCO_WDT_PM_OPS (&iTCO_wdt_pm) |
|
#else |
|
#define ITCO_WDT_PM_OPS NULL |
|
#endif /* CONFIG_PM_SLEEP */ |
|
|
|
static struct platform_driver iTCO_wdt_driver = { |
|
.probe = iTCO_wdt_probe, |
|
.driver = { |
|
.name = DRV_NAME, |
|
.pm = ITCO_WDT_PM_OPS, |
|
}, |
|
}; |
|
|
|
module_platform_driver(iTCO_wdt_driver); |
|
|
|
MODULE_AUTHOR("Wim Van Sebroeck <[email protected]>"); |
|
MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver"); |
|
MODULE_VERSION(DRV_VERSION); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("platform:" DRV_NAME);
|
|
|