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433 lines
11 KiB
433 lines
11 KiB
/* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D fb driver for sparc64 systems |
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* |
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* License: GPL |
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* |
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* Copyright (C) 2007 David S. Miller ([email protected]) |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/fb.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/of_device.h> |
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#include <asm/io.h> |
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/* XXX This device has a 'dev-comm' property which apparently is |
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* XXX a pointer into the openfirmware's address space which is |
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* XXX a shared area the kernel driver can use to keep OBP |
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* XXX informed about the current resolution setting. The idea |
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* XXX is that the kernel can change resolutions, and as long |
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* XXX as the values in the 'dev-comm' area are accurate then |
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* XXX OBP can still render text properly to the console. |
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* XXX |
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* XXX I'm still working out the layout of this and whether there |
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* XXX are any signatures we need to look for etc. |
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*/ |
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struct e3d_info { |
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struct fb_info *info; |
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struct pci_dev *pdev; |
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spinlock_t lock; |
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char __iomem *fb_base; |
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unsigned long fb_base_phys; |
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unsigned long fb8_buf_diff; |
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unsigned long regs_base_phys; |
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void __iomem *ramdac; |
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struct device_node *of_node; |
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unsigned int width; |
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unsigned int height; |
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unsigned int depth; |
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unsigned int fb_size; |
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u32 fb_base_reg; |
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u32 fb8_0_off; |
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u32 fb8_1_off; |
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u32 pseudo_palette[16]; |
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}; |
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static int e3d_get_props(struct e3d_info *ep) |
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{ |
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ep->width = of_getintprop_default(ep->of_node, "width", 0); |
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ep->height = of_getintprop_default(ep->of_node, "height", 0); |
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ep->depth = of_getintprop_default(ep->of_node, "depth", 8); |
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if (!ep->width || !ep->height) { |
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printk(KERN_ERR "e3d: Critical properties missing for %s\n", |
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pci_name(ep->pdev)); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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/* My XVR-500 comes up, at 1280x768 and a FB base register value of |
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* 0x04000000, the following video layout register values: |
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* |
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* RAMDAC_VID_WH 0x03ff04ff |
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* RAMDAC_VID_CFG 0x1a0b0088 |
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* RAMDAC_VID_32FB_0 0x04000000 |
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* RAMDAC_VID_32FB_1 0x04800000 |
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* RAMDAC_VID_8FB_0 0x05000000 |
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* RAMDAC_VID_8FB_1 0x05200000 |
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* RAMDAC_VID_XXXFB 0x05400000 |
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* RAMDAC_VID_YYYFB 0x05c00000 |
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* RAMDAC_VID_ZZZFB 0x05e00000 |
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*/ |
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/* Video layout registers */ |
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#define RAMDAC_VID_WH 0x00000070UL /* (height-1)<<16 | (width-1) */ |
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#define RAMDAC_VID_CFG 0x00000074UL /* 0x1a000088|(linesz_log2<<16) */ |
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#define RAMDAC_VID_32FB_0 0x00000078UL /* PCI base 32bpp FB buffer 0 */ |
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#define RAMDAC_VID_32FB_1 0x0000007cUL /* PCI base 32bpp FB buffer 1 */ |
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#define RAMDAC_VID_8FB_0 0x00000080UL /* PCI base 8bpp FB buffer 0 */ |
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#define RAMDAC_VID_8FB_1 0x00000084UL /* PCI base 8bpp FB buffer 1 */ |
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#define RAMDAC_VID_XXXFB 0x00000088UL /* PCI base of XXX FB */ |
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#define RAMDAC_VID_YYYFB 0x0000008cUL /* PCI base of YYY FB */ |
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#define RAMDAC_VID_ZZZFB 0x00000090UL /* PCI base of ZZZ FB */ |
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/* CLUT registers */ |
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#define RAMDAC_INDEX 0x000000bcUL |
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#define RAMDAC_DATA 0x000000c0UL |
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static void e3d_clut_write(struct e3d_info *ep, int index, u32 val) |
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{ |
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void __iomem *ramdac = ep->ramdac; |
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unsigned long flags; |
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spin_lock_irqsave(&ep->lock, flags); |
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writel(index, ramdac + RAMDAC_INDEX); |
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writel(val, ramdac + RAMDAC_DATA); |
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spin_unlock_irqrestore(&ep->lock, flags); |
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} |
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static int e3d_setcolreg(unsigned regno, |
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unsigned red, unsigned green, unsigned blue, |
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unsigned transp, struct fb_info *info) |
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{ |
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struct e3d_info *ep = info->par; |
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u32 red_8, green_8, blue_8; |
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u32 red_10, green_10, blue_10; |
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u32 value; |
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if (regno >= 256) |
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return 1; |
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red_8 = red >> 8; |
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green_8 = green >> 8; |
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blue_8 = blue >> 8; |
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value = (blue_8 << 24) | (green_8 << 16) | (red_8 << 8); |
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if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16) |
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((u32 *)info->pseudo_palette)[regno] = value; |
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red_10 = red >> 6; |
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green_10 = green >> 6; |
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blue_10 = blue >> 6; |
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value = (blue_10 << 20) | (green_10 << 10) | (red_10 << 0); |
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e3d_clut_write(ep, regno, value); |
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return 0; |
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} |
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/* XXX This is a bit of a hack. I can't figure out exactly how the |
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* XXX two 8bpp areas of the framebuffer work. I imagine there is |
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* XXX a WID attribute somewhere else in the framebuffer which tells |
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* XXX the ramdac which of the two 8bpp framebuffer regions to take |
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* XXX the pixel from. So, for now, render into both regions to make |
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* XXX sure the pixel shows up. |
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*/ |
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static void e3d_imageblit(struct fb_info *info, const struct fb_image *image) |
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{ |
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struct e3d_info *ep = info->par; |
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unsigned long flags; |
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spin_lock_irqsave(&ep->lock, flags); |
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cfb_imageblit(info, image); |
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info->screen_base += ep->fb8_buf_diff; |
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cfb_imageblit(info, image); |
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info->screen_base -= ep->fb8_buf_diff; |
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spin_unlock_irqrestore(&ep->lock, flags); |
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} |
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static void e3d_fillrect(struct fb_info *info, const struct fb_fillrect *rect) |
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{ |
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struct e3d_info *ep = info->par; |
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unsigned long flags; |
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spin_lock_irqsave(&ep->lock, flags); |
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cfb_fillrect(info, rect); |
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info->screen_base += ep->fb8_buf_diff; |
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cfb_fillrect(info, rect); |
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info->screen_base -= ep->fb8_buf_diff; |
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spin_unlock_irqrestore(&ep->lock, flags); |
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} |
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static void e3d_copyarea(struct fb_info *info, const struct fb_copyarea *area) |
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{ |
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struct e3d_info *ep = info->par; |
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unsigned long flags; |
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spin_lock_irqsave(&ep->lock, flags); |
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cfb_copyarea(info, area); |
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info->screen_base += ep->fb8_buf_diff; |
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cfb_copyarea(info, area); |
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info->screen_base -= ep->fb8_buf_diff; |
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spin_unlock_irqrestore(&ep->lock, flags); |
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} |
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static const struct fb_ops e3d_ops = { |
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.owner = THIS_MODULE, |
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.fb_setcolreg = e3d_setcolreg, |
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.fb_fillrect = e3d_fillrect, |
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.fb_copyarea = e3d_copyarea, |
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.fb_imageblit = e3d_imageblit, |
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}; |
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static int e3d_set_fbinfo(struct e3d_info *ep) |
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{ |
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struct fb_info *info = ep->info; |
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struct fb_var_screeninfo *var = &info->var; |
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info->flags = FBINFO_DEFAULT; |
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info->fbops = &e3d_ops; |
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info->screen_base = ep->fb_base; |
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info->screen_size = ep->fb_size; |
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info->pseudo_palette = ep->pseudo_palette; |
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/* Fill fix common fields */ |
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strlcpy(info->fix.id, "e3d", sizeof(info->fix.id)); |
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info->fix.smem_start = ep->fb_base_phys; |
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info->fix.smem_len = ep->fb_size; |
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info->fix.type = FB_TYPE_PACKED_PIXELS; |
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if (ep->depth == 32 || ep->depth == 24) |
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info->fix.visual = FB_VISUAL_TRUECOLOR; |
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else |
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info->fix.visual = FB_VISUAL_PSEUDOCOLOR; |
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var->xres = ep->width; |
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var->yres = ep->height; |
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var->xres_virtual = var->xres; |
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var->yres_virtual = var->yres; |
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var->bits_per_pixel = ep->depth; |
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var->red.offset = 8; |
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var->red.length = 8; |
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var->green.offset = 16; |
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var->green.length = 8; |
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var->blue.offset = 24; |
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var->blue.length = 8; |
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var->transp.offset = 0; |
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var->transp.length = 0; |
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if (fb_alloc_cmap(&info->cmap, 256, 0)) { |
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printk(KERN_ERR "e3d: Cannot allocate color map.\n"); |
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return -ENOMEM; |
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} |
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return 0; |
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} |
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static int e3d_pci_register(struct pci_dev *pdev, |
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const struct pci_device_id *ent) |
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{ |
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struct device_node *of_node; |
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const char *device_type; |
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struct fb_info *info; |
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struct e3d_info *ep; |
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unsigned int line_length; |
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int err; |
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of_node = pci_device_to_OF_node(pdev); |
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if (!of_node) { |
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printk(KERN_ERR "e3d: Cannot find OF node of %s\n", |
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pci_name(pdev)); |
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return -ENODEV; |
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} |
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device_type = of_get_property(of_node, "device_type", NULL); |
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if (!device_type) { |
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printk(KERN_INFO "e3d: Ignoring secondary output device " |
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"at %s\n", pci_name(pdev)); |
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return -ENODEV; |
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} |
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err = pci_enable_device(pdev); |
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if (err < 0) { |
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printk(KERN_ERR "e3d: Cannot enable PCI device %s\n", |
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pci_name(pdev)); |
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goto err_out; |
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} |
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info = framebuffer_alloc(sizeof(struct e3d_info), &pdev->dev); |
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if (!info) { |
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err = -ENOMEM; |
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goto err_disable; |
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} |
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ep = info->par; |
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ep->info = info; |
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ep->pdev = pdev; |
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spin_lock_init(&ep->lock); |
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ep->of_node = of_node; |
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/* Read the PCI base register of the frame buffer, which we |
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* need in order to interpret the RAMDAC_VID_*FB* values in |
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* the ramdac correctly. |
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*/ |
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pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, |
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&ep->fb_base_reg); |
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ep->fb_base_reg &= PCI_BASE_ADDRESS_MEM_MASK; |
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ep->regs_base_phys = pci_resource_start (pdev, 1); |
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err = pci_request_region(pdev, 1, "e3d regs"); |
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if (err < 0) { |
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printk("e3d: Cannot request region 1 for %s\n", |
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pci_name(pdev)); |
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goto err_release_fb; |
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} |
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ep->ramdac = ioremap(ep->regs_base_phys + 0x8000, 0x1000); |
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if (!ep->ramdac) { |
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err = -ENOMEM; |
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goto err_release_pci1; |
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} |
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ep->fb8_0_off = readl(ep->ramdac + RAMDAC_VID_8FB_0); |
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ep->fb8_0_off -= ep->fb_base_reg; |
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ep->fb8_1_off = readl(ep->ramdac + RAMDAC_VID_8FB_1); |
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ep->fb8_1_off -= ep->fb_base_reg; |
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ep->fb8_buf_diff = ep->fb8_1_off - ep->fb8_0_off; |
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ep->fb_base_phys = pci_resource_start (pdev, 0); |
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ep->fb_base_phys += ep->fb8_0_off; |
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err = pci_request_region(pdev, 0, "e3d framebuffer"); |
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if (err < 0) { |
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printk("e3d: Cannot request region 0 for %s\n", |
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pci_name(pdev)); |
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goto err_unmap_ramdac; |
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} |
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err = e3d_get_props(ep); |
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if (err) |
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goto err_release_pci0; |
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line_length = (readl(ep->ramdac + RAMDAC_VID_CFG) >> 16) & 0xff; |
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line_length = 1 << line_length; |
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switch (ep->depth) { |
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case 8: |
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info->fix.line_length = line_length; |
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break; |
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case 16: |
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info->fix.line_length = line_length * 2; |
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break; |
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case 24: |
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info->fix.line_length = line_length * 3; |
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break; |
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case 32: |
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info->fix.line_length = line_length * 4; |
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break; |
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} |
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ep->fb_size = info->fix.line_length * ep->height; |
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ep->fb_base = ioremap(ep->fb_base_phys, ep->fb_size); |
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if (!ep->fb_base) { |
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err = -ENOMEM; |
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goto err_release_pci0; |
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} |
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err = e3d_set_fbinfo(ep); |
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if (err) |
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goto err_unmap_fb; |
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pci_set_drvdata(pdev, info); |
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printk("e3d: Found device at %s\n", pci_name(pdev)); |
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err = register_framebuffer(info); |
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if (err < 0) { |
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printk(KERN_ERR "e3d: Could not register framebuffer %s\n", |
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pci_name(pdev)); |
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goto err_free_cmap; |
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} |
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return 0; |
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err_free_cmap: |
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fb_dealloc_cmap(&info->cmap); |
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err_unmap_fb: |
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iounmap(ep->fb_base); |
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err_release_pci0: |
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pci_release_region(pdev, 0); |
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err_unmap_ramdac: |
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iounmap(ep->ramdac); |
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err_release_pci1: |
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pci_release_region(pdev, 1); |
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err_release_fb: |
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framebuffer_release(info); |
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err_disable: |
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pci_disable_device(pdev); |
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err_out: |
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return err; |
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} |
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static const struct pci_device_id e3d_pci_table[] = { |
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{ PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a0), }, |
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{ PCI_DEVICE(0x1091, 0x7a0), }, |
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{ PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a2), }, |
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{ .vendor = PCI_VENDOR_ID_3DLABS, |
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.device = PCI_ANY_ID, |
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.subvendor = PCI_VENDOR_ID_3DLABS, |
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.subdevice = 0x0108, |
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}, |
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{ .vendor = PCI_VENDOR_ID_3DLABS, |
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.device = PCI_ANY_ID, |
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.subvendor = PCI_VENDOR_ID_3DLABS, |
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.subdevice = 0x0140, |
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}, |
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{ .vendor = PCI_VENDOR_ID_3DLABS, |
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.device = PCI_ANY_ID, |
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.subvendor = PCI_VENDOR_ID_3DLABS, |
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.subdevice = 0x1024, |
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}, |
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{ 0, } |
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}; |
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static struct pci_driver e3d_driver = { |
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.driver = { |
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.suppress_bind_attrs = true, |
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}, |
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.name = "e3d", |
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.id_table = e3d_pci_table, |
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.probe = e3d_pci_register, |
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}; |
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static int __init e3d_init(void) |
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{ |
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if (fb_get_options("e3d", NULL)) |
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return -ENODEV; |
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return pci_register_driver(&e3d_driver); |
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} |
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device_initcall(e3d_init);
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