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516 lines
12 KiB
516 lines
12 KiB
/* |
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* drivers/video/chipsfb.c -- frame buffer device for |
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* Chips & Technologies 65550 chip. |
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* |
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* Copyright (C) 1998-2002 Paul Mackerras |
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* |
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* This file is derived from the Powermac "chips" driver: |
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* Copyright (C) 1997 Fabio Riccardi. |
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* And from the frame buffer device for Open Firmware-initialized devices: |
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* Copyright (C) 1997 Geert Uytterhoeven. |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file COPYING in the main directory of this archive for |
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* more details. |
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*/ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/errno.h> |
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#include <linux/string.h> |
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#include <linux/mm.h> |
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#include <linux/vmalloc.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/fb.h> |
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#include <linux/pm.h> |
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#include <linux/init.h> |
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#include <linux/pci.h> |
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#include <linux/console.h> |
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#ifdef CONFIG_PMAC_BACKLIGHT |
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#include <asm/backlight.h> |
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#endif |
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/* |
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* Since we access the display with inb/outb to fixed port numbers, |
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* we can only handle one 6555x chip. -- paulus |
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*/ |
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#define write_ind(num, val, ap, dp) do { \ |
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outb((num), (ap)); outb((val), (dp)); \ |
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} while (0) |
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#define read_ind(num, var, ap, dp) do { \ |
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outb((num), (ap)); var = inb((dp)); \ |
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} while (0) |
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/* extension registers */ |
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#define write_xr(num, val) write_ind(num, val, 0x3d6, 0x3d7) |
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#define read_xr(num, var) read_ind(num, var, 0x3d6, 0x3d7) |
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/* flat panel registers */ |
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#define write_fr(num, val) write_ind(num, val, 0x3d0, 0x3d1) |
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#define read_fr(num, var) read_ind(num, var, 0x3d0, 0x3d1) |
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/* CRTC registers */ |
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#define write_cr(num, val) write_ind(num, val, 0x3d4, 0x3d5) |
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#define read_cr(num, var) read_ind(num, var, 0x3d4, 0x3d5) |
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/* graphics registers */ |
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#define write_gr(num, val) write_ind(num, val, 0x3ce, 0x3cf) |
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#define read_gr(num, var) read_ind(num, var, 0x3ce, 0x3cf) |
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/* sequencer registers */ |
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#define write_sr(num, val) write_ind(num, val, 0x3c4, 0x3c5) |
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#define read_sr(num, var) read_ind(num, var, 0x3c4, 0x3c5) |
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/* attribute registers - slightly strange */ |
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#define write_ar(num, val) do { \ |
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inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \ |
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} while (0) |
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#define read_ar(num, var) do { \ |
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inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \ |
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} while (0) |
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/* |
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* Exported functions |
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*/ |
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int chips_init(void); |
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static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *); |
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static int chipsfb_check_var(struct fb_var_screeninfo *var, |
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struct fb_info *info); |
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static int chipsfb_set_par(struct fb_info *info); |
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static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, |
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u_int transp, struct fb_info *info); |
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static int chipsfb_blank(int blank, struct fb_info *info); |
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static const struct fb_ops chipsfb_ops = { |
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.owner = THIS_MODULE, |
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.fb_check_var = chipsfb_check_var, |
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.fb_set_par = chipsfb_set_par, |
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.fb_setcolreg = chipsfb_setcolreg, |
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.fb_blank = chipsfb_blank, |
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.fb_fillrect = cfb_fillrect, |
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.fb_copyarea = cfb_copyarea, |
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.fb_imageblit = cfb_imageblit, |
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}; |
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static int chipsfb_check_var(struct fb_var_screeninfo *var, |
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struct fb_info *info) |
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{ |
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if (var->xres > 800 || var->yres > 600 |
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|| var->xres_virtual > 800 || var->yres_virtual > 600 |
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|| (var->bits_per_pixel != 8 && var->bits_per_pixel != 16) |
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|| var->nonstd |
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|| (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) |
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return -EINVAL; |
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var->xres = var->xres_virtual = 800; |
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var->yres = var->yres_virtual = 600; |
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return 0; |
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} |
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static int chipsfb_set_par(struct fb_info *info) |
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{ |
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if (info->var.bits_per_pixel == 16) { |
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write_cr(0x13, 200); // Set line length (doublewords) |
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write_xr(0x81, 0x14); // 15 bit (555) color mode |
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write_xr(0x82, 0x00); // Disable palettes |
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write_xr(0x20, 0x10); // 16 bit blitter mode |
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info->fix.line_length = 800*2; |
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info->fix.visual = FB_VISUAL_TRUECOLOR; |
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info->var.red.offset = 10; |
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info->var.green.offset = 5; |
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info->var.blue.offset = 0; |
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info->var.red.length = info->var.green.length = |
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info->var.blue.length = 5; |
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} else { |
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/* p->var.bits_per_pixel == 8 */ |
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write_cr(0x13, 100); // Set line length (doublewords) |
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write_xr(0x81, 0x12); // 8 bit color mode |
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write_xr(0x82, 0x08); // Graphics gamma enable |
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write_xr(0x20, 0x00); // 8 bit blitter mode |
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info->fix.line_length = 800; |
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info->fix.visual = FB_VISUAL_PSEUDOCOLOR; |
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info->var.red.offset = info->var.green.offset = |
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info->var.blue.offset = 0; |
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info->var.red.length = info->var.green.length = |
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info->var.blue.length = 8; |
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} |
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return 0; |
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} |
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static int chipsfb_blank(int blank, struct fb_info *info) |
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{ |
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return 1; /* get fb_blank to set the colormap to all black */ |
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} |
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static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, |
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u_int transp, struct fb_info *info) |
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{ |
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if (regno > 255) |
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return 1; |
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red >>= 8; |
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green >>= 8; |
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blue >>= 8; |
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outb(regno, 0x3c8); |
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udelay(1); |
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outb(red, 0x3c9); |
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outb(green, 0x3c9); |
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outb(blue, 0x3c9); |
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return 0; |
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} |
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struct chips_init_reg { |
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unsigned char addr; |
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unsigned char data; |
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}; |
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static struct chips_init_reg chips_init_sr[] = { |
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{ 0x00, 0x03 }, |
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{ 0x01, 0x01 }, |
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{ 0x02, 0x0f }, |
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{ 0x04, 0x0e } |
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}; |
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static struct chips_init_reg chips_init_gr[] = { |
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{ 0x05, 0x00 }, |
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{ 0x06, 0x0d }, |
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{ 0x08, 0xff } |
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}; |
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static struct chips_init_reg chips_init_ar[] = { |
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{ 0x10, 0x01 }, |
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{ 0x12, 0x0f }, |
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{ 0x13, 0x00 } |
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}; |
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static struct chips_init_reg chips_init_cr[] = { |
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{ 0x00, 0x7f }, |
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{ 0x01, 0x63 }, |
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{ 0x02, 0x63 }, |
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{ 0x03, 0x83 }, |
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{ 0x04, 0x66 }, |
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{ 0x05, 0x10 }, |
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{ 0x06, 0x72 }, |
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{ 0x07, 0x3e }, |
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{ 0x08, 0x00 }, |
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{ 0x09, 0x40 }, |
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{ 0x0c, 0x00 }, |
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{ 0x0d, 0x00 }, |
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{ 0x10, 0x59 }, |
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{ 0x11, 0x0d }, |
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{ 0x12, 0x57 }, |
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{ 0x13, 0x64 }, |
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{ 0x14, 0x00 }, |
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{ 0x15, 0x57 }, |
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{ 0x16, 0x73 }, |
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{ 0x17, 0xe3 }, |
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{ 0x18, 0xff }, |
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{ 0x30, 0x02 }, |
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{ 0x31, 0x02 }, |
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{ 0x32, 0x02 }, |
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{ 0x33, 0x02 }, |
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{ 0x40, 0x00 }, |
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{ 0x41, 0x00 }, |
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{ 0x40, 0x80 } |
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}; |
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static struct chips_init_reg chips_init_fr[] = { |
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{ 0x01, 0x02 }, |
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{ 0x03, 0x08 }, |
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{ 0x04, 0x81 }, |
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{ 0x05, 0x21 }, |
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{ 0x08, 0x0c }, |
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{ 0x0a, 0x74 }, |
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{ 0x0b, 0x11 }, |
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{ 0x10, 0x0c }, |
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{ 0x11, 0xe0 }, |
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/* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */ |
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{ 0x20, 0x63 }, |
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{ 0x21, 0x68 }, |
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{ 0x22, 0x19 }, |
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{ 0x23, 0x7f }, |
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{ 0x24, 0x68 }, |
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{ 0x26, 0x00 }, |
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{ 0x27, 0x0f }, |
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{ 0x30, 0x57 }, |
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{ 0x31, 0x58 }, |
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{ 0x32, 0x0d }, |
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{ 0x33, 0x72 }, |
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{ 0x34, 0x02 }, |
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{ 0x35, 0x22 }, |
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{ 0x36, 0x02 }, |
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{ 0x37, 0x00 } |
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}; |
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static struct chips_init_reg chips_init_xr[] = { |
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{ 0xce, 0x00 }, /* set default memory clock */ |
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{ 0xcc, 0x43 }, /* memory clock ratio */ |
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{ 0xcd, 0x18 }, |
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{ 0xce, 0xa1 }, |
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{ 0xc8, 0x84 }, |
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{ 0xc9, 0x0a }, |
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{ 0xca, 0x00 }, |
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{ 0xcb, 0x20 }, |
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{ 0xcf, 0x06 }, |
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{ 0xd0, 0x0e }, |
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{ 0x09, 0x01 }, |
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{ 0x0a, 0x02 }, |
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{ 0x0b, 0x01 }, |
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{ 0x20, 0x00 }, |
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{ 0x40, 0x03 }, |
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{ 0x41, 0x01 }, |
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{ 0x42, 0x00 }, |
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{ 0x80, 0x82 }, |
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{ 0x81, 0x12 }, |
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{ 0x82, 0x08 }, |
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{ 0xa0, 0x00 }, |
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{ 0xa8, 0x00 } |
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}; |
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static void chips_hw_init(void) |
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{ |
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int i; |
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for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i) |
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write_xr(chips_init_xr[i].addr, chips_init_xr[i].data); |
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outb(0x29, 0x3c2); /* set misc output reg */ |
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for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i) |
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write_sr(chips_init_sr[i].addr, chips_init_sr[i].data); |
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for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i) |
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write_gr(chips_init_gr[i].addr, chips_init_gr[i].data); |
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for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i) |
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write_ar(chips_init_ar[i].addr, chips_init_ar[i].data); |
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for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i) |
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write_cr(chips_init_cr[i].addr, chips_init_cr[i].data); |
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for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i) |
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write_fr(chips_init_fr[i].addr, chips_init_fr[i].data); |
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} |
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static const struct fb_fix_screeninfo chipsfb_fix = { |
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.id = "C&T 65550", |
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.type = FB_TYPE_PACKED_PIXELS, |
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.visual = FB_VISUAL_PSEUDOCOLOR, |
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.accel = FB_ACCEL_NONE, |
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.line_length = 800, |
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// FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB. |
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// * "3500" PowerBook G3 (the original PB G3) has 2MB. |
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// * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips. |
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// Motherboard actually supports 2MB -- there are two blank locations |
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// for a second pair of DRAMs. (Thanks, Apple!) |
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// * 3400 has 1MB (I think). Don't know if it's expandable. |
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// -- Tim Seufert |
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.smem_len = 0x100000, /* 1MB */ |
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}; |
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static const struct fb_var_screeninfo chipsfb_var = { |
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.xres = 800, |
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.yres = 600, |
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.xres_virtual = 800, |
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.yres_virtual = 600, |
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.bits_per_pixel = 8, |
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.red = { .length = 8 }, |
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.green = { .length = 8 }, |
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.blue = { .length = 8 }, |
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.height = -1, |
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.width = -1, |
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.vmode = FB_VMODE_NONINTERLACED, |
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.pixclock = 10000, |
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.left_margin = 16, |
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.right_margin = 16, |
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.upper_margin = 16, |
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.lower_margin = 16, |
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.hsync_len = 8, |
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.vsync_len = 8, |
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}; |
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static void init_chips(struct fb_info *p, unsigned long addr) |
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{ |
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memset(p->screen_base, 0, 0x100000); |
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p->fix = chipsfb_fix; |
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p->fix.smem_start = addr; |
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p->var = chipsfb_var; |
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p->fbops = &chipsfb_ops; |
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p->flags = FBINFO_DEFAULT; |
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fb_alloc_cmap(&p->cmap, 256, 0); |
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chips_hw_init(); |
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} |
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static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent) |
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{ |
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struct fb_info *p; |
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unsigned long addr; |
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unsigned short cmd; |
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int rc = -ENODEV; |
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if (pci_enable_device(dp) < 0) { |
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dev_err(&dp->dev, "Cannot enable PCI device\n"); |
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goto err_out; |
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} |
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if ((dp->resource[0].flags & IORESOURCE_MEM) == 0) |
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goto err_disable; |
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addr = pci_resource_start(dp, 0); |
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if (addr == 0) |
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goto err_disable; |
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p = framebuffer_alloc(0, &dp->dev); |
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if (p == NULL) { |
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rc = -ENOMEM; |
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goto err_disable; |
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} |
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if (pci_request_region(dp, 0, "chipsfb") != 0) { |
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dev_err(&dp->dev, "Cannot request framebuffer\n"); |
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rc = -EBUSY; |
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goto err_release_fb; |
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} |
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#ifdef __BIG_ENDIAN |
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addr += 0x800000; // Use big-endian aperture |
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#endif |
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/* we should use pci_enable_device here, but, |
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the device doesn't declare its I/O ports in its BARs |
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so pci_enable_device won't turn on I/O responses */ |
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pci_read_config_word(dp, PCI_COMMAND, &cmd); |
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cmd |= 3; /* enable memory and IO space */ |
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pci_write_config_word(dp, PCI_COMMAND, cmd); |
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#ifdef CONFIG_PMAC_BACKLIGHT |
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/* turn on the backlight */ |
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mutex_lock(&pmac_backlight_mutex); |
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if (pmac_backlight) { |
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pmac_backlight->props.power = FB_BLANK_UNBLANK; |
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backlight_update_status(pmac_backlight); |
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} |
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mutex_unlock(&pmac_backlight_mutex); |
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#endif /* CONFIG_PMAC_BACKLIGHT */ |
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#ifdef CONFIG_PPC |
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p->screen_base = ioremap_wc(addr, 0x200000); |
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#else |
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p->screen_base = ioremap(addr, 0x200000); |
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#endif |
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if (p->screen_base == NULL) { |
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dev_err(&dp->dev, "Cannot map framebuffer\n"); |
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rc = -ENOMEM; |
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goto err_release_pci; |
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} |
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pci_set_drvdata(dp, p); |
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init_chips(p, addr); |
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if (register_framebuffer(p) < 0) { |
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dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n"); |
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goto err_unmap; |
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} |
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dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer" |
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" (%dK RAM detected)\n", |
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p->node, p->fix.smem_len / 1024); |
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return 0; |
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err_unmap: |
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iounmap(p->screen_base); |
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err_release_pci: |
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pci_release_region(dp, 0); |
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err_release_fb: |
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framebuffer_release(p); |
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err_disable: |
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err_out: |
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return rc; |
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} |
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static void chipsfb_remove(struct pci_dev *dp) |
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{ |
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struct fb_info *p = pci_get_drvdata(dp); |
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if (p->screen_base == NULL) |
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return; |
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unregister_framebuffer(p); |
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iounmap(p->screen_base); |
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p->screen_base = NULL; |
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pci_release_region(dp, 0); |
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} |
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#ifdef CONFIG_PM |
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static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
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{ |
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struct fb_info *p = pci_get_drvdata(pdev); |
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if (state.event == pdev->dev.power.power_state.event) |
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return 0; |
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if (!(state.event & PM_EVENT_SLEEP)) |
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goto done; |
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console_lock(); |
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chipsfb_blank(1, p); |
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fb_set_suspend(p, 1); |
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console_unlock(); |
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done: |
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pdev->dev.power.power_state = state; |
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return 0; |
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} |
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static int chipsfb_pci_resume(struct pci_dev *pdev) |
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{ |
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struct fb_info *p = pci_get_drvdata(pdev); |
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console_lock(); |
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fb_set_suspend(p, 0); |
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chipsfb_blank(0, p); |
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console_unlock(); |
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pdev->dev.power.power_state = PMSG_ON; |
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return 0; |
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} |
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#endif /* CONFIG_PM */ |
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static struct pci_device_id chipsfb_pci_tbl[] = { |
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{ PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID }, |
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{ 0 } |
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}; |
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MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl); |
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static struct pci_driver chipsfb_driver = { |
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.name = "chipsfb", |
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.id_table = chipsfb_pci_tbl, |
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.probe = chipsfb_pci_init, |
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.remove = chipsfb_remove, |
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#ifdef CONFIG_PM |
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.suspend = chipsfb_pci_suspend, |
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.resume = chipsfb_pci_resume, |
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#endif |
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}; |
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int __init chips_init(void) |
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{ |
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if (fb_get_options("chipsfb", NULL)) |
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return -ENODEV; |
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return pci_register_driver(&chipsfb_driver); |
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} |
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module_init(chips_init); |
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static void __exit chipsfb_exit(void) |
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{ |
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pci_unregister_driver(&chipsfb_driver); |
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} |
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MODULE_LICENSE("GPL");
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