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608 lines
15 KiB
608 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Texas Instruments AM35x "glue layer" |
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* |
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* Copyright (c) 2010, by Texas Instruments |
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* |
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* Based on the DA8xx "glue layer" code. |
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* Copyright (c) 2008-2009, MontaVista Software, Inc. <[email protected]> |
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* |
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* This file is part of the Inventra Controller Driver for Linux. |
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*/ |
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#include <linux/module.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/platform_device.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/usb/usb_phy_generic.h> |
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#include <linux/platform_data/usb-omap.h> |
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#include "musb_core.h" |
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/* |
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* AM35x specific definitions |
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*/ |
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/* USB 2.0 OTG module registers */ |
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#define USB_REVISION_REG 0x00 |
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#define USB_CTRL_REG 0x04 |
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#define USB_STAT_REG 0x08 |
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#define USB_EMULATION_REG 0x0c |
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/* 0x10 Reserved */ |
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#define USB_AUTOREQ_REG 0x14 |
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#define USB_SRP_FIX_TIME_REG 0x18 |
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#define USB_TEARDOWN_REG 0x1c |
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#define EP_INTR_SRC_REG 0x20 |
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#define EP_INTR_SRC_SET_REG 0x24 |
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#define EP_INTR_SRC_CLEAR_REG 0x28 |
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#define EP_INTR_MASK_REG 0x2c |
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#define EP_INTR_MASK_SET_REG 0x30 |
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#define EP_INTR_MASK_CLEAR_REG 0x34 |
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#define EP_INTR_SRC_MASKED_REG 0x38 |
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#define CORE_INTR_SRC_REG 0x40 |
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#define CORE_INTR_SRC_SET_REG 0x44 |
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#define CORE_INTR_SRC_CLEAR_REG 0x48 |
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#define CORE_INTR_MASK_REG 0x4c |
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#define CORE_INTR_MASK_SET_REG 0x50 |
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#define CORE_INTR_MASK_CLEAR_REG 0x54 |
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#define CORE_INTR_SRC_MASKED_REG 0x58 |
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/* 0x5c Reserved */ |
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#define USB_END_OF_INTR_REG 0x60 |
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/* Control register bits */ |
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#define AM35X_SOFT_RESET_MASK 1 |
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/* USB interrupt register bits */ |
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#define AM35X_INTR_USB_SHIFT 16 |
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#define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT) |
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#define AM35X_INTR_DRVVBUS 0x100 |
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#define AM35X_INTR_RX_SHIFT 16 |
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#define AM35X_INTR_TX_SHIFT 0 |
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#define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */ |
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#define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */ |
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#define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT) |
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#define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT) |
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#define USB_MENTOR_CORE_OFFSET 0x400 |
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struct am35x_glue { |
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struct device *dev; |
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struct platform_device *musb; |
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struct platform_device *phy; |
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struct clk *phy_clk; |
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struct clk *clk; |
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}; |
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/* |
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* am35x_musb_enable - enable interrupts |
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*/ |
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static void am35x_musb_enable(struct musb *musb) |
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{ |
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void __iomem *reg_base = musb->ctrl_base; |
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u32 epmask; |
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/* Workaround: setup IRQs through both register sets. */ |
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epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) | |
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((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT); |
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musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); |
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musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); |
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/* Force the DRVVBUS IRQ so we can start polling for ID change. */ |
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musb_writel(reg_base, CORE_INTR_SRC_SET_REG, |
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AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT); |
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} |
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/* |
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* am35x_musb_disable - disable HDRC and flush interrupts |
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*/ |
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static void am35x_musb_disable(struct musb *musb) |
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{ |
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void __iomem *reg_base = musb->ctrl_base; |
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musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); |
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musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, |
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AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK); |
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musb_writel(reg_base, USB_END_OF_INTR_REG, 0); |
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} |
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#define portstate(stmt) stmt |
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static void am35x_musb_set_vbus(struct musb *musb, int is_on) |
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{ |
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WARN_ON(is_on && is_peripheral_active(musb)); |
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} |
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#define POLL_SECONDS 2 |
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static void otg_timer(struct timer_list *t) |
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{ |
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struct musb *musb = from_timer(musb, t, dev_timer); |
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void __iomem *mregs = musb->mregs; |
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u8 devctl; |
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unsigned long flags; |
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/* |
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* We poll because AM35x's won't expose several OTG-critical |
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* status change events (from the transceiver) otherwise. |
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*/ |
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devctl = musb_readb(mregs, MUSB_DEVCTL); |
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dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, |
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usb_otg_state_string(musb->xceiv->otg->state)); |
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spin_lock_irqsave(&musb->lock, flags); |
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switch (musb->xceiv->otg->state) { |
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case OTG_STATE_A_WAIT_BCON: |
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devctl &= ~MUSB_DEVCTL_SESSION; |
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musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); |
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devctl = musb_readb(musb->mregs, MUSB_DEVCTL); |
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if (devctl & MUSB_DEVCTL_BDEVICE) { |
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musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
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MUSB_DEV_MODE(musb); |
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} else { |
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musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
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MUSB_HST_MODE(musb); |
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} |
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break; |
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case OTG_STATE_A_WAIT_VFALL: |
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musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; |
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musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG, |
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MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT); |
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break; |
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case OTG_STATE_B_IDLE: |
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devctl = musb_readb(mregs, MUSB_DEVCTL); |
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if (devctl & MUSB_DEVCTL_BDEVICE) |
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mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ); |
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else |
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musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
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break; |
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default: |
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break; |
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} |
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spin_unlock_irqrestore(&musb->lock, flags); |
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} |
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static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout) |
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{ |
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static unsigned long last_timer; |
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if (timeout == 0) |
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timeout = jiffies + msecs_to_jiffies(3); |
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/* Never idle if active, or when VBUS timeout is not set as host */ |
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if (musb->is_active || (musb->a_wait_bcon == 0 && |
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musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) { |
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dev_dbg(musb->controller, "%s active, deleting timer\n", |
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usb_otg_state_string(musb->xceiv->otg->state)); |
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del_timer(&musb->dev_timer); |
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last_timer = jiffies; |
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return; |
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} |
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if (time_after(last_timer, timeout) && timer_pending(&musb->dev_timer)) { |
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dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n"); |
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return; |
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} |
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last_timer = timeout; |
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dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n", |
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usb_otg_state_string(musb->xceiv->otg->state), |
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jiffies_to_msecs(timeout - jiffies)); |
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mod_timer(&musb->dev_timer, timeout); |
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} |
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static irqreturn_t am35x_musb_interrupt(int irq, void *hci) |
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{ |
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struct musb *musb = hci; |
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void __iomem *reg_base = musb->ctrl_base; |
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struct device *dev = musb->controller; |
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struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
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struct omap_musb_board_data *data = plat->board_data; |
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unsigned long flags; |
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irqreturn_t ret = IRQ_NONE; |
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u32 epintr, usbintr; |
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spin_lock_irqsave(&musb->lock, flags); |
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/* Get endpoint interrupts */ |
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epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); |
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if (epintr) { |
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musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr); |
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musb->int_rx = |
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(epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT; |
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musb->int_tx = |
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(epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT; |
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} |
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/* Get usb core interrupts */ |
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usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG); |
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if (!usbintr && !epintr) |
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goto eoi; |
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if (usbintr) { |
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musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr); |
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musb->int_usb = |
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(usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT; |
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} |
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/* |
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* DRVVBUS IRQs are the only proxy we have (a very poor one!) for |
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* AM35x's missing ID change IRQ. We need an ID change IRQ to |
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* switch appropriately between halves of the OTG state machine. |
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* Managing DEVCTL.SESSION per Mentor docs requires that we know its |
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* value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. |
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* Also, DRVVBUS pulses for SRP (but not at 5V) ... |
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*/ |
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if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) { |
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int drvvbus = musb_readl(reg_base, USB_STAT_REG); |
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void __iomem *mregs = musb->mregs; |
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u8 devctl = musb_readb(mregs, MUSB_DEVCTL); |
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int err; |
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err = musb->int_usb & MUSB_INTR_VBUSERROR; |
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if (err) { |
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/* |
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* The Mentor core doesn't debounce VBUS as needed |
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* to cope with device connect current spikes. This |
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* means it's not uncommon for bus-powered devices |
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* to get VBUS errors during enumeration. |
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* |
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* This is a workaround, but newer RTL from Mentor |
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* seems to allow a better one: "re"-starting sessions |
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* without waiting for VBUS to stop registering in |
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* devctl. |
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*/ |
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musb->int_usb &= ~MUSB_INTR_VBUSERROR; |
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musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; |
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mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ); |
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WARNING("VBUS error workaround (delay coming)\n"); |
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} else if (drvvbus) { |
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MUSB_HST_MODE(musb); |
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musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; |
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portstate(musb->port1_status |= USB_PORT_STAT_POWER); |
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del_timer(&musb->dev_timer); |
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} else { |
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musb->is_active = 0; |
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MUSB_DEV_MODE(musb); |
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musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
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portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); |
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} |
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/* NOTE: this must complete power-on within 100 ms. */ |
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dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", |
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drvvbus ? "on" : "off", |
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usb_otg_state_string(musb->xceiv->otg->state), |
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err ? " ERROR" : "", |
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devctl); |
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ret = IRQ_HANDLED; |
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} |
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/* Drop spurious RX and TX if device is disconnected */ |
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if (musb->int_usb & MUSB_INTR_DISCONNECT) { |
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musb->int_tx = 0; |
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musb->int_rx = 0; |
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} |
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if (musb->int_tx || musb->int_rx || musb->int_usb) |
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ret |= musb_interrupt(musb); |
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eoi: |
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/* EOI needs to be written for the IRQ to be re-asserted. */ |
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if (ret == IRQ_HANDLED || epintr || usbintr) { |
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/* clear level interrupt */ |
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if (data->clear_irq) |
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data->clear_irq(); |
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/* write EOI */ |
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musb_writel(reg_base, USB_END_OF_INTR_REG, 0); |
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} |
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/* Poll for ID change */ |
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if (musb->xceiv->otg->state == OTG_STATE_B_IDLE) |
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mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ); |
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spin_unlock_irqrestore(&musb->lock, flags); |
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return ret; |
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} |
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static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode) |
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{ |
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struct device *dev = musb->controller; |
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struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
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struct omap_musb_board_data *data = plat->board_data; |
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int retval = 0; |
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if (data->set_mode) |
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data->set_mode(musb_mode); |
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else |
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retval = -EIO; |
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return retval; |
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} |
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static int am35x_musb_init(struct musb *musb) |
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{ |
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struct device *dev = musb->controller; |
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struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
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struct omap_musb_board_data *data = plat->board_data; |
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void __iomem *reg_base = musb->ctrl_base; |
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u32 rev; |
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musb->mregs += USB_MENTOR_CORE_OFFSET; |
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/* Returns zero if e.g. not clocked */ |
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rev = musb_readl(reg_base, USB_REVISION_REG); |
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if (!rev) |
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return -ENODEV; |
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musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); |
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if (IS_ERR_OR_NULL(musb->xceiv)) |
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return -EPROBE_DEFER; |
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timer_setup(&musb->dev_timer, otg_timer, 0); |
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/* Reset the musb */ |
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if (data->reset) |
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data->reset(); |
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/* Reset the controller */ |
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musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK); |
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/* Start the on-chip PHY and its PLL. */ |
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if (data->set_phy_power) |
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data->set_phy_power(1); |
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msleep(5); |
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musb->isr = am35x_musb_interrupt; |
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/* clear level interrupt */ |
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if (data->clear_irq) |
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data->clear_irq(); |
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return 0; |
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} |
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static int am35x_musb_exit(struct musb *musb) |
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{ |
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struct device *dev = musb->controller; |
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struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
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struct omap_musb_board_data *data = plat->board_data; |
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del_timer_sync(&musb->dev_timer); |
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/* Shutdown the on-chip PHY and its PLL. */ |
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if (data->set_phy_power) |
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data->set_phy_power(0); |
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usb_put_phy(musb->xceiv); |
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return 0; |
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} |
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/* AM35x supports only 32bit read operation */ |
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static void am35x_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) |
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{ |
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void __iomem *fifo = hw_ep->fifo; |
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u32 val; |
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int i; |
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/* Read for 32bit-aligned destination address */ |
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if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) { |
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readsl(fifo, dst, len >> 2); |
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dst += len & ~0x03; |
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len &= 0x03; |
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} |
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/* |
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* Now read the remaining 1 to 3 byte or complete length if |
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* unaligned address. |
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*/ |
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if (len > 4) { |
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for (i = 0; i < (len >> 2); i++) { |
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*(u32 *) dst = musb_readl(fifo, 0); |
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dst += 4; |
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} |
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len &= 0x03; |
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} |
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if (len > 0) { |
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val = musb_readl(fifo, 0); |
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memcpy(dst, &val, len); |
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} |
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} |
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static const struct musb_platform_ops am35x_ops = { |
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.quirks = MUSB_DMA_INVENTRA | MUSB_INDEXED_EP, |
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.init = am35x_musb_init, |
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.exit = am35x_musb_exit, |
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.read_fifo = am35x_read_fifo, |
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#ifdef CONFIG_USB_INVENTRA_DMA |
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.dma_init = musbhs_dma_controller_create, |
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.dma_exit = musbhs_dma_controller_destroy, |
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#endif |
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.enable = am35x_musb_enable, |
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.disable = am35x_musb_disable, |
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.set_mode = am35x_musb_set_mode, |
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.try_idle = am35x_musb_try_idle, |
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.set_vbus = am35x_musb_set_vbus, |
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}; |
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static const struct platform_device_info am35x_dev_info = { |
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.name = "musb-hdrc", |
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.id = PLATFORM_DEVID_AUTO, |
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.dma_mask = DMA_BIT_MASK(32), |
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}; |
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static int am35x_probe(struct platform_device *pdev) |
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{ |
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struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev); |
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struct platform_device *musb; |
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struct am35x_glue *glue; |
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struct platform_device_info pinfo; |
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struct clk *phy_clk; |
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struct clk *clk; |
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int ret = -ENOMEM; |
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glue = kzalloc(sizeof(*glue), GFP_KERNEL); |
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if (!glue) |
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goto err0; |
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phy_clk = clk_get(&pdev->dev, "fck"); |
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if (IS_ERR(phy_clk)) { |
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dev_err(&pdev->dev, "failed to get PHY clock\n"); |
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ret = PTR_ERR(phy_clk); |
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goto err3; |
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} |
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clk = clk_get(&pdev->dev, "ick"); |
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if (IS_ERR(clk)) { |
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dev_err(&pdev->dev, "failed to get clock\n"); |
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ret = PTR_ERR(clk); |
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goto err4; |
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} |
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ret = clk_enable(phy_clk); |
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if (ret) { |
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dev_err(&pdev->dev, "failed to enable PHY clock\n"); |
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goto err5; |
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} |
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ret = clk_enable(clk); |
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if (ret) { |
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dev_err(&pdev->dev, "failed to enable clock\n"); |
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goto err6; |
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} |
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glue->dev = &pdev->dev; |
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glue->phy_clk = phy_clk; |
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glue->clk = clk; |
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pdata->platform_ops = &am35x_ops; |
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glue->phy = usb_phy_generic_register(); |
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if (IS_ERR(glue->phy)) { |
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ret = PTR_ERR(glue->phy); |
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goto err7; |
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} |
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platform_set_drvdata(pdev, glue); |
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pinfo = am35x_dev_info; |
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pinfo.parent = &pdev->dev; |
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pinfo.res = pdev->resource; |
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pinfo.num_res = pdev->num_resources; |
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pinfo.data = pdata; |
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pinfo.size_data = sizeof(*pdata); |
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glue->musb = musb = platform_device_register_full(&pinfo); |
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if (IS_ERR(musb)) { |
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ret = PTR_ERR(musb); |
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dev_err(&pdev->dev, "failed to register musb device: %d\n", ret); |
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goto err8; |
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} |
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return 0; |
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err8: |
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usb_phy_generic_unregister(glue->phy); |
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err7: |
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clk_disable(clk); |
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err6: |
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clk_disable(phy_clk); |
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err5: |
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clk_put(clk); |
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err4: |
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clk_put(phy_clk); |
|
|
|
err3: |
|
kfree(glue); |
|
|
|
err0: |
|
return ret; |
|
} |
|
|
|
static int am35x_remove(struct platform_device *pdev) |
|
{ |
|
struct am35x_glue *glue = platform_get_drvdata(pdev); |
|
|
|
platform_device_unregister(glue->musb); |
|
usb_phy_generic_unregister(glue->phy); |
|
clk_disable(glue->clk); |
|
clk_disable(glue->phy_clk); |
|
clk_put(glue->clk); |
|
clk_put(glue->phy_clk); |
|
kfree(glue); |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int am35x_suspend(struct device *dev) |
|
{ |
|
struct am35x_glue *glue = dev_get_drvdata(dev); |
|
struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
|
struct omap_musb_board_data *data = plat->board_data; |
|
|
|
/* Shutdown the on-chip PHY and its PLL. */ |
|
if (data->set_phy_power) |
|
data->set_phy_power(0); |
|
|
|
clk_disable(glue->phy_clk); |
|
clk_disable(glue->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static int am35x_resume(struct device *dev) |
|
{ |
|
struct am35x_glue *glue = dev_get_drvdata(dev); |
|
struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
|
struct omap_musb_board_data *data = plat->board_data; |
|
int ret; |
|
|
|
/* Start the on-chip PHY and its PLL. */ |
|
if (data->set_phy_power) |
|
data->set_phy_power(1); |
|
|
|
ret = clk_enable(glue->phy_clk); |
|
if (ret) { |
|
dev_err(dev, "failed to enable PHY clock\n"); |
|
return ret; |
|
} |
|
|
|
ret = clk_enable(glue->clk); |
|
if (ret) { |
|
dev_err(dev, "failed to enable clock\n"); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
static SIMPLE_DEV_PM_OPS(am35x_pm_ops, am35x_suspend, am35x_resume); |
|
|
|
static struct platform_driver am35x_driver = { |
|
.probe = am35x_probe, |
|
.remove = am35x_remove, |
|
.driver = { |
|
.name = "musb-am35x", |
|
.pm = &am35x_pm_ops, |
|
}, |
|
}; |
|
|
|
MODULE_DESCRIPTION("AM35x MUSB Glue Layer"); |
|
MODULE_AUTHOR("Ajay Kumar Gupta <[email protected]>"); |
|
MODULE_LICENSE("GPL v2"); |
|
module_platform_driver(am35x_driver);
|
|
|