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25 KiB
895 lines
25 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
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/* |
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* core_intr.c - DesignWare HS OTG Controller common interrupt handling |
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* |
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* Copyright (C) 2004-2013 Synopsys, Inc. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions, and the following disclaimer, |
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* without modification. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The names of the above-listed copyright holders may not be used |
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* to endorse or promote products derived from this software without |
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* specific prior written permission. |
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* |
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* ALTERNATIVELY, this software may be distributed under the terms of the |
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* GNU General Public License ("GPL") as published by the Free Software |
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* Foundation; either version 2 of the License, or (at your option) any |
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* later version. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS |
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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/* |
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* This file contains the common interrupt handlers |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/moduleparam.h> |
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#include <linux/spinlock.h> |
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#include <linux/interrupt.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <linux/usb.h> |
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#include <linux/usb/hcd.h> |
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#include <linux/usb/ch11.h> |
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|
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#include "core.h" |
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#include "hcd.h" |
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static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg) |
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{ |
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switch (hsotg->op_state) { |
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case OTG_STATE_A_HOST: |
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return "a_host"; |
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case OTG_STATE_A_SUSPEND: |
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return "a_suspend"; |
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case OTG_STATE_A_PERIPHERAL: |
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return "a_peripheral"; |
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case OTG_STATE_B_PERIPHERAL: |
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return "b_peripheral"; |
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case OTG_STATE_B_HOST: |
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return "b_host"; |
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default: |
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return "unknown"; |
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} |
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} |
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|
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/** |
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* dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts. |
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* When the PRTINT interrupt fires, there are certain status bits in the Host |
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* Port that needs to get cleared. |
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* |
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* @hsotg: Programming view of DWC_otg controller |
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*/ |
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static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) |
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{ |
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u32 hprt0 = dwc2_readl(hsotg, HPRT0); |
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|
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if (hprt0 & HPRT0_ENACHG) { |
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hprt0 &= ~HPRT0_ENA; |
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dwc2_writel(hsotg, hprt0, HPRT0); |
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} |
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} |
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|
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/** |
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* dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message |
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* |
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* @hsotg: Programming view of DWC_otg controller |
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*/ |
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static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg) |
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{ |
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/* Clear interrupt */ |
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dwc2_writel(hsotg, GINTSTS_MODEMIS, GINTSTS); |
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dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n", |
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dwc2_is_host_mode(hsotg) ? "Host" : "Device"); |
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} |
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|
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/** |
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* dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG |
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* Interrupt Register (GOTGINT) to determine what interrupt has occurred. |
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* |
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* @hsotg: Programming view of DWC_otg controller |
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*/ |
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static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) |
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{ |
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u32 gotgint; |
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u32 gotgctl; |
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u32 gintmsk; |
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|
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gotgint = dwc2_readl(hsotg, GOTGINT); |
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gotgctl = dwc2_readl(hsotg, GOTGCTL); |
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dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, |
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dwc2_op_state_str(hsotg)); |
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|
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if (gotgint & GOTGINT_SES_END_DET) { |
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dev_dbg(hsotg->dev, |
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" ++OTG Interrupt: Session End Detected++ (%s)\n", |
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dwc2_op_state_str(hsotg)); |
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gotgctl = dwc2_readl(hsotg, GOTGCTL); |
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if (dwc2_is_device_mode(hsotg)) |
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dwc2_hsotg_disconnect(hsotg); |
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if (hsotg->op_state == OTG_STATE_B_HOST) { |
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hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
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} else { |
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/* |
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* If not B_HOST and Device HNP still set, HNP did |
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* not succeed! |
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*/ |
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if (gotgctl & GOTGCTL_DEVHNPEN) { |
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dev_dbg(hsotg->dev, "Session End Detected\n"); |
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dev_err(hsotg->dev, |
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"Device Not Connected/Responding!\n"); |
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} |
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|
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/* |
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* If Session End Detected the B-Cable has been |
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* disconnected |
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*/ |
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/* Reset to a clean state */ |
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hsotg->lx_state = DWC2_L0; |
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} |
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gotgctl = dwc2_readl(hsotg, GOTGCTL); |
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gotgctl &= ~GOTGCTL_DEVHNPEN; |
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dwc2_writel(hsotg, gotgctl, GOTGCTL); |
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} |
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if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) { |
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dev_dbg(hsotg->dev, |
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" ++OTG Interrupt: Session Request Success Status Change++\n"); |
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gotgctl = dwc2_readl(hsotg, GOTGCTL); |
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if (gotgctl & GOTGCTL_SESREQSCS) { |
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if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS && |
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hsotg->params.i2c_enable) { |
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hsotg->srp_success = 1; |
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} else { |
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/* Clear Session Request */ |
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gotgctl = dwc2_readl(hsotg, GOTGCTL); |
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gotgctl &= ~GOTGCTL_SESREQ; |
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dwc2_writel(hsotg, gotgctl, GOTGCTL); |
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} |
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} |
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} |
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if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) { |
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/* |
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* Print statements during the HNP interrupt handling |
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* can cause it to fail |
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*/ |
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gotgctl = dwc2_readl(hsotg, GOTGCTL); |
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/* |
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* WA for 3.00a- HW is not setting cur_mode, even sometimes |
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* this does not help |
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*/ |
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if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) |
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udelay(100); |
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if (gotgctl & GOTGCTL_HSTNEGSCS) { |
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if (dwc2_is_host_mode(hsotg)) { |
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hsotg->op_state = OTG_STATE_B_HOST; |
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/* |
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* Need to disable SOF interrupt immediately. |
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* When switching from device to host, the PCD |
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* interrupt handler won't handle the interrupt |
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* if host mode is already set. The HCD |
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* interrupt handler won't get called if the |
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* HCD state is HALT. This means that the |
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* interrupt does not get handled and Linux |
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* complains loudly. |
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*/ |
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gintmsk = dwc2_readl(hsotg, GINTMSK); |
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gintmsk &= ~GINTSTS_SOF; |
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dwc2_writel(hsotg, gintmsk, GINTMSK); |
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/* |
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* Call callback function with spin lock |
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* released |
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*/ |
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spin_unlock(&hsotg->lock); |
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|
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/* Initialize the Core for Host mode */ |
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dwc2_hcd_start(hsotg); |
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spin_lock(&hsotg->lock); |
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hsotg->op_state = OTG_STATE_B_HOST; |
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} |
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} else { |
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gotgctl = dwc2_readl(hsotg, GOTGCTL); |
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gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN); |
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dwc2_writel(hsotg, gotgctl, GOTGCTL); |
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dev_dbg(hsotg->dev, "HNP Failed\n"); |
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dev_err(hsotg->dev, |
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"Device Not Connected/Responding\n"); |
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} |
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} |
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if (gotgint & GOTGINT_HST_NEG_DET) { |
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/* |
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* The disconnect interrupt is set at the same time as |
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* Host Negotiation Detected. During the mode switch all |
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* interrupts are cleared so the disconnect interrupt |
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* handler will not get executed. |
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*/ |
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dev_dbg(hsotg->dev, |
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" ++OTG Interrupt: Host Negotiation Detected++ (%s)\n", |
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(dwc2_is_host_mode(hsotg) ? "Host" : "Device")); |
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if (dwc2_is_device_mode(hsotg)) { |
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dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n", |
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hsotg->op_state); |
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spin_unlock(&hsotg->lock); |
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dwc2_hcd_disconnect(hsotg, false); |
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spin_lock(&hsotg->lock); |
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hsotg->op_state = OTG_STATE_A_PERIPHERAL; |
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} else { |
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/* Need to disable SOF interrupt immediately */ |
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gintmsk = dwc2_readl(hsotg, GINTMSK); |
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gintmsk &= ~GINTSTS_SOF; |
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dwc2_writel(hsotg, gintmsk, GINTMSK); |
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spin_unlock(&hsotg->lock); |
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dwc2_hcd_start(hsotg); |
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spin_lock(&hsotg->lock); |
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hsotg->op_state = OTG_STATE_A_HOST; |
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} |
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} |
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if (gotgint & GOTGINT_A_DEV_TOUT_CHG) |
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dev_dbg(hsotg->dev, |
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" ++OTG Interrupt: A-Device Timeout Change++\n"); |
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if (gotgint & GOTGINT_DBNCE_DONE) |
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dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n"); |
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/* Clear GOTGINT */ |
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dwc2_writel(hsotg, gotgint, GOTGINT); |
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} |
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/** |
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* dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status |
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* Change Interrupt |
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* |
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* @hsotg: Programming view of DWC_otg controller |
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* |
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* Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a |
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* Device to Host Mode transition or a Host to Device Mode transition. This only |
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* occurs when the cable is connected/removed from the PHY connector. |
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*/ |
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static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) |
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{ |
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u32 gintmsk; |
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|
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/* Clear interrupt */ |
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dwc2_writel(hsotg, GINTSTS_CONIDSTSCHNG, GINTSTS); |
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|
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/* Need to disable SOF interrupt immediately */ |
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gintmsk = dwc2_readl(hsotg, GINTMSK); |
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gintmsk &= ~GINTSTS_SOF; |
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dwc2_writel(hsotg, gintmsk, GINTMSK); |
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dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", |
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dwc2_is_host_mode(hsotg) ? "Host" : "Device"); |
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/* |
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* Need to schedule a work, as there are possible DELAY function calls. |
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*/ |
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if (hsotg->wq_otg) |
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queue_work(hsotg->wq_otg, &hsotg->wf_otg); |
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} |
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|
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/** |
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* dwc2_handle_session_req_intr() - This interrupt indicates that a device is |
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* initiating the Session Request Protocol to request the host to turn on bus |
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* power so a new session can begin |
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* |
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* @hsotg: Programming view of DWC_otg controller |
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* |
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* This handler responds by turning on bus power. If the DWC_otg controller is |
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* in low power mode, this handler brings the controller out of low power mode |
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* before turning on bus power. |
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*/ |
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static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) |
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{ |
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int ret; |
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u32 hprt0; |
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/* Clear interrupt */ |
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dwc2_writel(hsotg, GINTSTS_SESSREQINT, GINTSTS); |
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dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n", |
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hsotg->lx_state); |
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if (dwc2_is_device_mode(hsotg)) { |
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if (hsotg->lx_state == DWC2_L2) { |
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if (hsotg->in_ppd) { |
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ret = dwc2_exit_partial_power_down(hsotg, 0, |
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true); |
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if (ret) |
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dev_err(hsotg->dev, |
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"exit power_down failed\n"); |
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} |
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|
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/* Exit gadget mode clock gating. */ |
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if (hsotg->params.power_down == |
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DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended) |
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dwc2_gadget_exit_clock_gating(hsotg, 0); |
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} |
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|
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/* |
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* Report disconnect if there is any previous session |
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* established |
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*/ |
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dwc2_hsotg_disconnect(hsotg); |
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} else { |
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/* Turn on the port power bit. */ |
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hprt0 = dwc2_read_hprt0(hsotg); |
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hprt0 |= HPRT0_PWR; |
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dwc2_writel(hsotg, hprt0, HPRT0); |
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/* Connect hcd after port power is set. */ |
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dwc2_hcd_connect(hsotg); |
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} |
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} |
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|
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/** |
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* dwc2_wakeup_from_lpm_l1 - Exit the device from LPM L1 state |
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* |
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* @hsotg: Programming view of DWC_otg controller |
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* |
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*/ |
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static void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg) |
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{ |
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u32 glpmcfg; |
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u32 i = 0; |
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|
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if (hsotg->lx_state != DWC2_L1) { |
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dev_err(hsotg->dev, "Core isn't in DWC2_L1 state\n"); |
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return; |
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} |
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|
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glpmcfg = dwc2_readl(hsotg, GLPMCFG); |
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if (dwc2_is_device_mode(hsotg)) { |
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dev_dbg(hsotg->dev, "Exit from L1 state\n"); |
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glpmcfg &= ~GLPMCFG_ENBLSLPM; |
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glpmcfg &= ~GLPMCFG_HIRD_THRES_EN; |
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dwc2_writel(hsotg, glpmcfg, GLPMCFG); |
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|
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do { |
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glpmcfg = dwc2_readl(hsotg, GLPMCFG); |
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|
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if (!(glpmcfg & (GLPMCFG_COREL1RES_MASK | |
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GLPMCFG_L1RESUMEOK | GLPMCFG_SLPSTS))) |
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break; |
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|
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udelay(1); |
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} while (++i < 200); |
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|
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if (i == 200) { |
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dev_err(hsotg->dev, "Failed to exit L1 sleep state in 200us.\n"); |
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return; |
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} |
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dwc2_gadget_init_lpm(hsotg); |
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} else { |
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/* TODO */ |
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dev_err(hsotg->dev, "Host side LPM is not supported.\n"); |
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return; |
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} |
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|
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/* Change to L0 state */ |
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hsotg->lx_state = DWC2_L0; |
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|
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/* Inform gadget to exit from L1 */ |
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call_gadget(hsotg, resume); |
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} |
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|
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/* |
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* This interrupt indicates that the DWC_otg controller has detected a |
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* resume or remote wakeup sequence. If the DWC_otg controller is in |
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* low power mode, the handler must brings the controller out of low |
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* power mode. The controller automatically begins resume signaling. |
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* The handler schedules a time to stop resume signaling. |
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*/ |
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static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) |
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{ |
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int ret; |
|
|
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/* Clear interrupt */ |
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dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS); |
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|
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dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n"); |
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dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state); |
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|
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if (hsotg->lx_state == DWC2_L1) { |
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dwc2_wakeup_from_lpm_l1(hsotg); |
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return; |
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} |
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|
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if (dwc2_is_device_mode(hsotg)) { |
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dev_dbg(hsotg->dev, "DSTS=0x%0x\n", |
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dwc2_readl(hsotg, DSTS)); |
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if (hsotg->lx_state == DWC2_L2) { |
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if (hsotg->in_ppd) { |
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u32 dctl = dwc2_readl(hsotg, DCTL); |
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/* Clear Remote Wakeup Signaling */ |
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dctl &= ~DCTL_RMTWKUPSIG; |
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dwc2_writel(hsotg, dctl, DCTL); |
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ret = dwc2_exit_partial_power_down(hsotg, 1, |
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true); |
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if (ret) |
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dev_err(hsotg->dev, |
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"exit partial_power_down failed\n"); |
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call_gadget(hsotg, resume); |
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} |
|
|
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/* Exit gadget mode clock gating. */ |
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if (hsotg->params.power_down == |
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DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended) |
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dwc2_gadget_exit_clock_gating(hsotg, 0); |
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} else { |
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/* Change to L0 state */ |
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hsotg->lx_state = DWC2_L0; |
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} |
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} else { |
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if (hsotg->lx_state == DWC2_L2) { |
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if (hsotg->in_ppd) { |
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ret = dwc2_exit_partial_power_down(hsotg, 1, |
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true); |
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if (ret) |
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dev_err(hsotg->dev, |
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"exit partial_power_down failed\n"); |
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} |
|
|
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if (hsotg->params.power_down == |
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DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended) |
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dwc2_host_exit_clock_gating(hsotg, 1); |
|
|
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/* |
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* If we've got this quirk then the PHY is stuck upon |
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* wakeup. Assert reset. This will propagate out and |
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* eventually we'll re-enumerate the device. Not great |
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* but the best we can do. We can't call phy_reset() |
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* at interrupt time but there's no hurry, so we'll |
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* schedule it for later. |
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*/ |
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if (hsotg->reset_phy_on_wake) |
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dwc2_host_schedule_phy_reset(hsotg); |
|
|
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mod_timer(&hsotg->wkp_timer, |
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jiffies + msecs_to_jiffies(71)); |
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} else { |
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/* Change to L0 state */ |
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hsotg->lx_state = DWC2_L0; |
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} |
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} |
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} |
|
|
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/* |
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* This interrupt indicates that a device has been disconnected from the |
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* root port |
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*/ |
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static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg) |
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{ |
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dwc2_writel(hsotg, GINTSTS_DISCONNINT, GINTSTS); |
|
|
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dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n", |
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dwc2_is_host_mode(hsotg) ? "Host" : "Device", |
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dwc2_op_state_str(hsotg)); |
|
|
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if (hsotg->op_state == OTG_STATE_A_HOST) |
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dwc2_hcd_disconnect(hsotg, false); |
|
} |
|
|
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/* |
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* This interrupt indicates that SUSPEND state has been detected on the USB. |
|
* |
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* For HNP the USB Suspend interrupt signals the change from "a_peripheral" |
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* to "a_host". |
|
* |
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* When power management is enabled the core will be put in low power mode. |
|
*/ |
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static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) |
|
{ |
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u32 dsts; |
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int ret; |
|
|
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/* Clear interrupt */ |
|
dwc2_writel(hsotg, GINTSTS_USBSUSP, GINTSTS); |
|
|
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dev_dbg(hsotg->dev, "USB SUSPEND\n"); |
|
|
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if (dwc2_is_device_mode(hsotg)) { |
|
/* |
|
* Check the Device status register to determine if the Suspend |
|
* state is active |
|
*/ |
|
dsts = dwc2_readl(hsotg, DSTS); |
|
dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts); |
|
dev_dbg(hsotg->dev, |
|
"DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n", |
|
!!(dsts & DSTS_SUSPSTS), |
|
hsotg->hw_params.power_optimized, |
|
hsotg->hw_params.hibernation); |
|
|
|
/* Ignore suspend request before enumeration */ |
|
if (!dwc2_is_device_connected(hsotg)) { |
|
dev_dbg(hsotg->dev, |
|
"ignore suspend request before enumeration\n"); |
|
return; |
|
} |
|
if (dsts & DSTS_SUSPSTS) { |
|
switch (hsotg->params.power_down) { |
|
case DWC2_POWER_DOWN_PARAM_PARTIAL: |
|
ret = dwc2_enter_partial_power_down(hsotg); |
|
if (ret) |
|
dev_err(hsotg->dev, |
|
"enter partial_power_down failed\n"); |
|
|
|
udelay(100); |
|
|
|
/* Ask phy to be suspended */ |
|
if (!IS_ERR_OR_NULL(hsotg->uphy)) |
|
usb_phy_set_suspend(hsotg->uphy, true); |
|
break; |
|
case DWC2_POWER_DOWN_PARAM_HIBERNATION: |
|
ret = dwc2_enter_hibernation(hsotg, 0); |
|
if (ret) |
|
dev_err(hsotg->dev, |
|
"enter hibernation failed\n"); |
|
break; |
|
case DWC2_POWER_DOWN_PARAM_NONE: |
|
/* |
|
* If neither hibernation nor partial power down are supported, |
|
* clock gating is used to save power. |
|
*/ |
|
if (!hsotg->params.no_clock_gating) |
|
dwc2_gadget_enter_clock_gating(hsotg); |
|
} |
|
|
|
/* |
|
* Change to L2 (suspend) state before releasing |
|
* spinlock |
|
*/ |
|
hsotg->lx_state = DWC2_L2; |
|
|
|
/* Call gadget suspend callback */ |
|
call_gadget(hsotg, suspend); |
|
} |
|
} else { |
|
if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) { |
|
dev_dbg(hsotg->dev, "a_peripheral->a_host\n"); |
|
|
|
/* Change to L2 (suspend) state */ |
|
hsotg->lx_state = DWC2_L2; |
|
/* Clear the a_peripheral flag, back to a_host */ |
|
spin_unlock(&hsotg->lock); |
|
dwc2_hcd_start(hsotg); |
|
spin_lock(&hsotg->lock); |
|
hsotg->op_state = OTG_STATE_A_HOST; |
|
} |
|
} |
|
} |
|
|
|
/** |
|
* dwc2_handle_lpm_intr - GINTSTS_LPMTRANRCVD Interrupt handler |
|
* |
|
* @hsotg: Programming view of DWC_otg controller |
|
* |
|
*/ |
|
static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg) |
|
{ |
|
u32 glpmcfg; |
|
u32 pcgcctl; |
|
u32 hird; |
|
u32 hird_thres; |
|
u32 hird_thres_en; |
|
u32 enslpm; |
|
|
|
/* Clear interrupt */ |
|
dwc2_writel(hsotg, GINTSTS_LPMTRANRCVD, GINTSTS); |
|
|
|
glpmcfg = dwc2_readl(hsotg, GLPMCFG); |
|
|
|
if (!(glpmcfg & GLPMCFG_LPMCAP)) { |
|
dev_err(hsotg->dev, "Unexpected LPM interrupt\n"); |
|
return; |
|
} |
|
|
|
hird = (glpmcfg & GLPMCFG_HIRD_MASK) >> GLPMCFG_HIRD_SHIFT; |
|
hird_thres = (glpmcfg & GLPMCFG_HIRD_THRES_MASK & |
|
~GLPMCFG_HIRD_THRES_EN) >> GLPMCFG_HIRD_THRES_SHIFT; |
|
hird_thres_en = glpmcfg & GLPMCFG_HIRD_THRES_EN; |
|
enslpm = glpmcfg & GLPMCFG_ENBLSLPM; |
|
|
|
if (dwc2_is_device_mode(hsotg)) { |
|
dev_dbg(hsotg->dev, "HIRD_THRES_EN = %d\n", hird_thres_en); |
|
|
|
if (hird_thres_en && hird >= hird_thres) { |
|
dev_dbg(hsotg->dev, "L1 with utmi_l1_suspend_n\n"); |
|
} else if (enslpm) { |
|
dev_dbg(hsotg->dev, "L1 with utmi_sleep_n\n"); |
|
} else { |
|
dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n"); |
|
|
|
pcgcctl = dwc2_readl(hsotg, PCGCTL); |
|
pcgcctl |= PCGCTL_ENBL_SLEEP_GATING; |
|
dwc2_writel(hsotg, pcgcctl, PCGCTL); |
|
} |
|
/** |
|
* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) |
|
*/ |
|
udelay(10); |
|
|
|
glpmcfg = dwc2_readl(hsotg, GLPMCFG); |
|
|
|
if (glpmcfg & GLPMCFG_SLPSTS) { |
|
/* Save the current state */ |
|
hsotg->lx_state = DWC2_L1; |
|
dev_dbg(hsotg->dev, |
|
"Core is in L1 sleep glpmcfg=%08x\n", glpmcfg); |
|
|
|
/* Inform gadget that we are in L1 state */ |
|
call_gadget(hsotg, suspend); |
|
} |
|
} |
|
} |
|
|
|
#define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \ |
|
GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \ |
|
GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \ |
|
GINTSTS_USBSUSP | GINTSTS_PRTINT | \ |
|
GINTSTS_LPMTRANRCVD) |
|
|
|
/* |
|
* This function returns the Core Interrupt register |
|
*/ |
|
static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg) |
|
{ |
|
u32 gintsts; |
|
u32 gintmsk; |
|
u32 gahbcfg; |
|
u32 gintmsk_common = GINTMSK_COMMON; |
|
|
|
gintsts = dwc2_readl(hsotg, GINTSTS); |
|
gintmsk = dwc2_readl(hsotg, GINTMSK); |
|
gahbcfg = dwc2_readl(hsotg, GAHBCFG); |
|
|
|
/* If any common interrupts set */ |
|
if (gintsts & gintmsk_common) |
|
dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n", |
|
gintsts, gintmsk); |
|
|
|
if (gahbcfg & GAHBCFG_GLBL_INTR_EN) |
|
return gintsts & gintmsk & gintmsk_common; |
|
else |
|
return 0; |
|
} |
|
|
|
/** |
|
* dwc_handle_gpwrdn_disc_det() - Handles the gpwrdn disconnect detect. |
|
* Exits hibernation without restoring registers. |
|
* |
|
* @hsotg: Programming view of DWC_otg controller |
|
* @gpwrdn: GPWRDN register |
|
*/ |
|
static inline void dwc_handle_gpwrdn_disc_det(struct dwc2_hsotg *hsotg, |
|
u32 gpwrdn) |
|
{ |
|
u32 gpwrdn_tmp; |
|
|
|
/* Switch-on voltage to the core */ |
|
gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); |
|
gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH; |
|
dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); |
|
udelay(5); |
|
|
|
/* Reset core */ |
|
gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); |
|
gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN; |
|
dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); |
|
udelay(5); |
|
|
|
/* Disable Power Down Clamp */ |
|
gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); |
|
gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP; |
|
dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); |
|
udelay(5); |
|
|
|
/* Deassert reset core */ |
|
gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); |
|
gpwrdn_tmp |= GPWRDN_PWRDNRSTN; |
|
dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); |
|
udelay(5); |
|
|
|
/* Disable PMU interrupt */ |
|
gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); |
|
gpwrdn_tmp &= ~GPWRDN_PMUINTSEL; |
|
dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); |
|
|
|
/* De-assert Wakeup Logic */ |
|
gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); |
|
gpwrdn_tmp &= ~GPWRDN_PMUACTV; |
|
dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); |
|
|
|
hsotg->hibernated = 0; |
|
hsotg->bus_suspended = 0; |
|
|
|
if (gpwrdn & GPWRDN_IDSTS) { |
|
hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
|
dwc2_core_init(hsotg, false); |
|
dwc2_enable_global_interrupts(hsotg); |
|
dwc2_hsotg_core_init_disconnected(hsotg, false); |
|
dwc2_hsotg_core_connect(hsotg); |
|
} else { |
|
hsotg->op_state = OTG_STATE_A_HOST; |
|
|
|
/* Initialize the Core for Host mode */ |
|
dwc2_core_init(hsotg, false); |
|
dwc2_enable_global_interrupts(hsotg); |
|
dwc2_hcd_start(hsotg); |
|
} |
|
} |
|
|
|
/* |
|
* GPWRDN interrupt handler. |
|
* |
|
* The GPWRDN interrupts are those that occur in both Host and |
|
* Device mode while core is in hibernated state. |
|
*/ |
|
static int dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg) |
|
{ |
|
u32 gpwrdn; |
|
int linestate; |
|
int ret = 0; |
|
|
|
gpwrdn = dwc2_readl(hsotg, GPWRDN); |
|
/* clear all interrupt */ |
|
dwc2_writel(hsotg, gpwrdn, GPWRDN); |
|
linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT; |
|
dev_dbg(hsotg->dev, |
|
"%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__, |
|
gpwrdn); |
|
|
|
if ((gpwrdn & GPWRDN_DISCONN_DET) && |
|
(gpwrdn & GPWRDN_DISCONN_DET_MSK) && !linestate) { |
|
dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__); |
|
/* |
|
* Call disconnect detect function to exit from |
|
* hibernation |
|
*/ |
|
dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn); |
|
} else if ((gpwrdn & GPWRDN_LNSTSCHG) && |
|
(gpwrdn & GPWRDN_LNSTSCHG_MSK) && linestate) { |
|
dev_dbg(hsotg->dev, "%s: GPWRDN_LNSTSCHG\n", __func__); |
|
if (hsotg->hw_params.hibernation && |
|
hsotg->hibernated) { |
|
if (gpwrdn & GPWRDN_IDSTS) { |
|
ret = dwc2_exit_hibernation(hsotg, 0, 0, 0); |
|
if (ret) |
|
dev_err(hsotg->dev, |
|
"exit hibernation failed.\n"); |
|
call_gadget(hsotg, resume); |
|
} else { |
|
ret = dwc2_exit_hibernation(hsotg, 1, 0, 1); |
|
if (ret) |
|
dev_err(hsotg->dev, |
|
"exit hibernation failed.\n"); |
|
} |
|
} |
|
} else if ((gpwrdn & GPWRDN_RST_DET) && |
|
(gpwrdn & GPWRDN_RST_DET_MSK)) { |
|
dev_dbg(hsotg->dev, "%s: GPWRDN_RST_DET\n", __func__); |
|
if (!linestate) { |
|
ret = dwc2_exit_hibernation(hsotg, 0, 1, 0); |
|
if (ret) |
|
dev_err(hsotg->dev, |
|
"exit hibernation failed.\n"); |
|
} |
|
} else if ((gpwrdn & GPWRDN_STS_CHGINT) && |
|
(gpwrdn & GPWRDN_STS_CHGINT_MSK)) { |
|
dev_dbg(hsotg->dev, "%s: GPWRDN_STS_CHGINT\n", __func__); |
|
/* |
|
* As GPWRDN_STS_CHGINT exit from hibernation flow is |
|
* the same as in GPWRDN_DISCONN_DET flow. Call |
|
* disconnect detect helper function to exit from |
|
* hibernation. |
|
*/ |
|
dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn); |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
/* |
|
* Common interrupt handler |
|
* |
|
* The common interrupts are those that occur in both Host and Device mode. |
|
* This handler handles the following interrupts: |
|
* - Mode Mismatch Interrupt |
|
* - OTG Interrupt |
|
* - Connector ID Status Change Interrupt |
|
* - Disconnect Interrupt |
|
* - Session Request Interrupt |
|
* - Resume / Remote Wakeup Detected Interrupt |
|
* - Suspend Interrupt |
|
*/ |
|
irqreturn_t dwc2_handle_common_intr(int irq, void *dev) |
|
{ |
|
struct dwc2_hsotg *hsotg = dev; |
|
u32 gintsts; |
|
irqreturn_t retval = IRQ_NONE; |
|
|
|
spin_lock(&hsotg->lock); |
|
|
|
if (!dwc2_is_controller_alive(hsotg)) { |
|
dev_warn(hsotg->dev, "Controller is dead\n"); |
|
goto out; |
|
} |
|
|
|
/* Reading current frame number value in device or host modes. */ |
|
if (dwc2_is_device_mode(hsotg)) |
|
hsotg->frame_number = (dwc2_readl(hsotg, DSTS) |
|
& DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT; |
|
else |
|
hsotg->frame_number = (dwc2_readl(hsotg, HFNUM) |
|
& HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; |
|
|
|
gintsts = dwc2_read_common_intr(hsotg); |
|
if (gintsts & ~GINTSTS_PRTINT) |
|
retval = IRQ_HANDLED; |
|
|
|
/* In case of hibernated state gintsts must not work */ |
|
if (hsotg->hibernated) { |
|
dwc2_handle_gpwrdn_intr(hsotg); |
|
retval = IRQ_HANDLED; |
|
goto out; |
|
} |
|
|
|
if (gintsts & GINTSTS_MODEMIS) |
|
dwc2_handle_mode_mismatch_intr(hsotg); |
|
if (gintsts & GINTSTS_OTGINT) |
|
dwc2_handle_otg_intr(hsotg); |
|
if (gintsts & GINTSTS_CONIDSTSCHNG) |
|
dwc2_handle_conn_id_status_change_intr(hsotg); |
|
if (gintsts & GINTSTS_DISCONNINT) |
|
dwc2_handle_disconnect_intr(hsotg); |
|
if (gintsts & GINTSTS_SESSREQINT) |
|
dwc2_handle_session_req_intr(hsotg); |
|
if (gintsts & GINTSTS_WKUPINT) |
|
dwc2_handle_wakeup_detected_intr(hsotg); |
|
if (gintsts & GINTSTS_USBSUSP) |
|
dwc2_handle_usb_suspend_intr(hsotg); |
|
if (gintsts & GINTSTS_LPMTRANRCVD) |
|
dwc2_handle_lpm_intr(hsotg); |
|
|
|
if (gintsts & GINTSTS_PRTINT) { |
|
/* |
|
* The port interrupt occurs while in device mode with HPRT0 |
|
* Port Enable/Disable |
|
*/ |
|
if (dwc2_is_device_mode(hsotg)) { |
|
dev_dbg(hsotg->dev, |
|
" --Port interrupt received in Device mode--\n"); |
|
dwc2_handle_usb_port_intr(hsotg); |
|
retval = IRQ_HANDLED; |
|
} |
|
} |
|
|
|
out: |
|
spin_unlock(&hsotg->lock); |
|
return retval; |
|
}
|
|
|