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494 lines
13 KiB
494 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* R-Car SYSC Power management support |
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* |
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* Copyright (C) 2014 Magnus Damm |
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* Copyright (C) 2015-2017 Glider bvba |
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*/ |
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#include <linux/clk/renesas.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/mm.h> |
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#include <linux/of_address.h> |
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#include <linux/pm_domain.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/soc/renesas/rcar-sysc.h> |
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#include "rcar-sysc.h" |
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/* SYSC Common */ |
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#define SYSCSR 0x00 /* SYSC Status Register */ |
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#define SYSCISR 0x04 /* Interrupt Status Register */ |
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#define SYSCISCR 0x08 /* Interrupt Status Clear Register */ |
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#define SYSCIER 0x0c /* Interrupt Enable Register */ |
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#define SYSCIMR 0x10 /* Interrupt Mask Register */ |
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/* SYSC Status Register */ |
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#define SYSCSR_PONENB 1 /* Ready for power resume requests */ |
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#define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */ |
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/* |
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* Power Control Register Offsets inside the register block for each domain |
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* Note: The "CR" registers for ARM cores exist on H1 only |
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* Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2 |
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* Use PSCI on R-Car Gen3 |
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*/ |
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#define PWRSR_OFFS 0x00 /* Power Status Register */ |
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#define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */ |
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#define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */ |
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#define PWRONCR_OFFS 0x0c /* Power Resume Control Register */ |
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#define PWRONSR_OFFS 0x10 /* Power Resume Status Register */ |
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#define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */ |
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#define SYSCSR_TIMEOUT 100 |
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#define SYSCSR_DELAY_US 1 |
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#define PWRER_RETRIES 100 |
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#define PWRER_DELAY_US 1 |
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#define SYSCISR_TIMEOUT 1000 |
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#define SYSCISR_DELAY_US 1 |
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#define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */ |
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struct rcar_sysc_ch { |
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u16 chan_offs; |
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u8 chan_bit; |
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u8 isr_bit; |
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}; |
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static void __iomem *rcar_sysc_base; |
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static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */ |
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static u32 rcar_sysc_extmask_offs, rcar_sysc_extmask_val; |
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static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on) |
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{ |
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unsigned int sr_bit, reg_offs; |
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u32 val; |
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int ret; |
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if (on) { |
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sr_bit = SYSCSR_PONENB; |
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reg_offs = PWRONCR_OFFS; |
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} else { |
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sr_bit = SYSCSR_POFFENB; |
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reg_offs = PWROFFCR_OFFS; |
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} |
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/* Wait until SYSC is ready to accept a power request */ |
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ret = readl_poll_timeout_atomic(rcar_sysc_base + SYSCSR, val, |
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val & BIT(sr_bit), SYSCSR_DELAY_US, |
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SYSCSR_TIMEOUT); |
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if (ret) |
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return -EAGAIN; |
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/* Submit power shutoff or power resume request */ |
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iowrite32(BIT(sysc_ch->chan_bit), |
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rcar_sysc_base + sysc_ch->chan_offs + reg_offs); |
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return 0; |
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} |
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static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on) |
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{ |
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unsigned int isr_mask = BIT(sysc_ch->isr_bit); |
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unsigned int chan_mask = BIT(sysc_ch->chan_bit); |
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unsigned int status, k; |
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unsigned long flags; |
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int ret; |
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spin_lock_irqsave(&rcar_sysc_lock, flags); |
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/* |
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* Mask external power requests for CPU or 3DG domains |
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*/ |
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if (rcar_sysc_extmask_val) { |
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iowrite32(rcar_sysc_extmask_val, |
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rcar_sysc_base + rcar_sysc_extmask_offs); |
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} |
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/* |
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* The interrupt source needs to be enabled, but masked, to prevent the |
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* CPU from receiving it. |
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*/ |
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iowrite32(ioread32(rcar_sysc_base + SYSCIMR) | isr_mask, |
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rcar_sysc_base + SYSCIMR); |
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iowrite32(ioread32(rcar_sysc_base + SYSCIER) | isr_mask, |
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rcar_sysc_base + SYSCIER); |
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iowrite32(isr_mask, rcar_sysc_base + SYSCISCR); |
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/* Submit power shutoff or resume request until it was accepted */ |
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for (k = 0; k < PWRER_RETRIES; k++) { |
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ret = rcar_sysc_pwr_on_off(sysc_ch, on); |
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if (ret) |
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goto out; |
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status = ioread32(rcar_sysc_base + |
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sysc_ch->chan_offs + PWRER_OFFS); |
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if (!(status & chan_mask)) |
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break; |
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udelay(PWRER_DELAY_US); |
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} |
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if (k == PWRER_RETRIES) { |
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ret = -EIO; |
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goto out; |
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} |
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/* Wait until the power shutoff or resume request has completed * */ |
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ret = readl_poll_timeout_atomic(rcar_sysc_base + SYSCISR, status, |
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status & isr_mask, SYSCISR_DELAY_US, |
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SYSCISR_TIMEOUT); |
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if (ret) |
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ret = -EIO; |
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iowrite32(isr_mask, rcar_sysc_base + SYSCISCR); |
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out: |
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if (rcar_sysc_extmask_val) |
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iowrite32(0, rcar_sysc_base + rcar_sysc_extmask_offs); |
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spin_unlock_irqrestore(&rcar_sysc_lock, flags); |
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pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off", |
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sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret); |
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return ret; |
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} |
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static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch) |
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{ |
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unsigned int st; |
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st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS); |
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if (st & BIT(sysc_ch->chan_bit)) |
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return true; |
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return false; |
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} |
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struct rcar_sysc_pd { |
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struct generic_pm_domain genpd; |
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struct rcar_sysc_ch ch; |
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unsigned int flags; |
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char name[]; |
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}; |
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static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d) |
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{ |
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return container_of(d, struct rcar_sysc_pd, genpd); |
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} |
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static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd) |
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{ |
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struct rcar_sysc_pd *pd = to_rcar_pd(genpd); |
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pr_debug("%s: %s\n", __func__, genpd->name); |
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return rcar_sysc_power(&pd->ch, false); |
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} |
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static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd) |
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{ |
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struct rcar_sysc_pd *pd = to_rcar_pd(genpd); |
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pr_debug("%s: %s\n", __func__, genpd->name); |
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return rcar_sysc_power(&pd->ch, true); |
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} |
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static bool has_cpg_mstp; |
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static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd) |
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{ |
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struct generic_pm_domain *genpd = &pd->genpd; |
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const char *name = pd->genpd.name; |
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int error; |
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if (pd->flags & PD_CPU) { |
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/* |
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* This domain contains a CPU core and therefore it should |
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* only be turned off if the CPU is not in use. |
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*/ |
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pr_debug("PM domain %s contains %s\n", name, "CPU"); |
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genpd->flags |= GENPD_FLAG_ALWAYS_ON; |
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} else if (pd->flags & PD_SCU) { |
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/* |
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* This domain contains an SCU and cache-controller, and |
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* therefore it should only be turned off if the CPU cores are |
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* not in use. |
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*/ |
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pr_debug("PM domain %s contains %s\n", name, "SCU"); |
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genpd->flags |= GENPD_FLAG_ALWAYS_ON; |
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} else if (pd->flags & PD_NO_CR) { |
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/* |
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* This domain cannot be turned off. |
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*/ |
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genpd->flags |= GENPD_FLAG_ALWAYS_ON; |
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} |
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if (!(pd->flags & (PD_CPU | PD_SCU))) { |
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/* Enable Clock Domain for I/O devices */ |
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genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; |
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if (has_cpg_mstp) { |
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genpd->attach_dev = cpg_mstp_attach_dev; |
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genpd->detach_dev = cpg_mstp_detach_dev; |
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} else { |
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genpd->attach_dev = cpg_mssr_attach_dev; |
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genpd->detach_dev = cpg_mssr_detach_dev; |
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} |
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} |
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genpd->power_off = rcar_sysc_pd_power_off; |
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genpd->power_on = rcar_sysc_pd_power_on; |
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if (pd->flags & (PD_CPU | PD_NO_CR)) { |
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/* Skip CPUs (handled by SMP code) and areas without control */ |
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pr_debug("%s: Not touching %s\n", __func__, genpd->name); |
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goto finalize; |
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} |
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if (!rcar_sysc_power_is_off(&pd->ch)) { |
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pr_debug("%s: %s is already powered\n", __func__, genpd->name); |
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goto finalize; |
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} |
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rcar_sysc_power(&pd->ch, true); |
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finalize: |
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error = pm_genpd_init(genpd, &simple_qos_governor, false); |
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if (error) |
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pr_err("Failed to init PM domain %s: %d\n", name, error); |
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return error; |
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} |
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static const struct of_device_id rcar_sysc_matches[] __initconst = { |
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#ifdef CONFIG_SYSC_R8A7742 |
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{ .compatible = "renesas,r8a7742-sysc", .data = &r8a7742_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A7743 |
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{ .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info }, |
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/* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */ |
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{ .compatible = "renesas,r8a7744-sysc", .data = &r8a7743_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A7745 |
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{ .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A77470 |
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{ .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A774A1 |
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{ .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A774B1 |
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{ .compatible = "renesas,r8a774b1-sysc", .data = &r8a774b1_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A774C0 |
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{ .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A774E1 |
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{ .compatible = "renesas,r8a774e1-sysc", .data = &r8a774e1_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A7779 |
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{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A7790 |
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{ .compatible = "renesas,r8a7790-sysc", .data = &r8a7790_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A7791 |
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{ .compatible = "renesas,r8a7791-sysc", .data = &r8a7791_sysc_info }, |
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/* R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. */ |
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{ .compatible = "renesas,r8a7793-sysc", .data = &r8a7791_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A7792 |
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{ .compatible = "renesas,r8a7792-sysc", .data = &r8a7792_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A7794 |
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{ .compatible = "renesas,r8a7794-sysc", .data = &r8a7794_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A7795 |
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{ .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A77960 |
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{ .compatible = "renesas,r8a7796-sysc", .data = &r8a77960_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A77961 |
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{ .compatible = "renesas,r8a77961-sysc", .data = &r8a77961_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A77965 |
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{ .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A77970 |
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{ .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A77980 |
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{ .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A77990 |
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{ .compatible = "renesas,r8a77990-sysc", .data = &r8a77990_sysc_info }, |
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#endif |
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#ifdef CONFIG_SYSC_R8A77995 |
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{ .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info }, |
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#endif |
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{ /* sentinel */ } |
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}; |
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struct rcar_pm_domains { |
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struct genpd_onecell_data onecell_data; |
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struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1]; |
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}; |
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static struct genpd_onecell_data *rcar_sysc_onecell_data; |
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static int __init rcar_sysc_pd_init(void) |
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{ |
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const struct rcar_sysc_info *info; |
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const struct of_device_id *match; |
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struct rcar_pm_domains *domains; |
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struct device_node *np; |
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void __iomem *base; |
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unsigned int i; |
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int error; |
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np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match); |
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if (!np) |
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return -ENODEV; |
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info = match->data; |
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if (info->init) { |
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error = info->init(); |
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if (error) |
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goto out_put; |
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} |
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has_cpg_mstp = of_find_compatible_node(NULL, NULL, |
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"renesas,cpg-mstp-clocks"); |
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base = of_iomap(np, 0); |
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if (!base) { |
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pr_warn("%pOF: Cannot map regs\n", np); |
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error = -ENOMEM; |
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goto out_put; |
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} |
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rcar_sysc_base = base; |
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/* Optional External Request Mask Register */ |
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rcar_sysc_extmask_offs = info->extmask_offs; |
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rcar_sysc_extmask_val = info->extmask_val; |
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domains = kzalloc(sizeof(*domains), GFP_KERNEL); |
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if (!domains) { |
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error = -ENOMEM; |
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goto out_put; |
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} |
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domains->onecell_data.domains = domains->domains; |
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domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains); |
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rcar_sysc_onecell_data = &domains->onecell_data; |
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for (i = 0; i < info->num_areas; i++) { |
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const struct rcar_sysc_area *area = &info->areas[i]; |
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struct rcar_sysc_pd *pd; |
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size_t n; |
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if (!area->name) { |
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/* Skip NULLified area */ |
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continue; |
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} |
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n = strlen(area->name) + 1; |
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pd = kzalloc(sizeof(*pd) + n, GFP_KERNEL); |
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if (!pd) { |
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error = -ENOMEM; |
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goto out_put; |
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} |
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memcpy(pd->name, area->name, n); |
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pd->genpd.name = pd->name; |
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pd->ch.chan_offs = area->chan_offs; |
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pd->ch.chan_bit = area->chan_bit; |
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pd->ch.isr_bit = area->isr_bit; |
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pd->flags = area->flags; |
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error = rcar_sysc_pd_setup(pd); |
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if (error) |
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goto out_put; |
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domains->domains[area->isr_bit] = &pd->genpd; |
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if (area->parent < 0) |
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continue; |
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error = pm_genpd_add_subdomain(domains->domains[area->parent], |
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&pd->genpd); |
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if (error) { |
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pr_warn("Failed to add PM subdomain %s to parent %u\n", |
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area->name, area->parent); |
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goto out_put; |
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} |
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} |
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error = of_genpd_add_provider_onecell(np, &domains->onecell_data); |
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if (!error) |
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of_node_set_flag(np, OF_POPULATED); |
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out_put: |
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of_node_put(np); |
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return error; |
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} |
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early_initcall(rcar_sysc_pd_init); |
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void __init rcar_sysc_nullify(struct rcar_sysc_area *areas, |
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unsigned int num_areas, u8 id) |
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{ |
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unsigned int i; |
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for (i = 0; i < num_areas; i++) |
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if (areas[i].isr_bit == id) { |
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areas[i].name = NULL; |
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return; |
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} |
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} |
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#ifdef CONFIG_ARCH_R8A7779 |
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static int rcar_sysc_power_cpu(unsigned int idx, bool on) |
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{ |
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struct generic_pm_domain *genpd; |
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struct rcar_sysc_pd *pd; |
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unsigned int i; |
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if (!rcar_sysc_onecell_data) |
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return -ENODEV; |
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for (i = 0; i < rcar_sysc_onecell_data->num_domains; i++) { |
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genpd = rcar_sysc_onecell_data->domains[i]; |
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if (!genpd) |
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continue; |
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pd = to_rcar_pd(genpd); |
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if (!(pd->flags & PD_CPU) || pd->ch.chan_bit != idx) |
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continue; |
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return rcar_sysc_power(&pd->ch, on); |
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} |
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return -ENOENT; |
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} |
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int rcar_sysc_power_down_cpu(unsigned int cpu) |
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{ |
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return rcar_sysc_power_cpu(cpu, false); |
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} |
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int rcar_sysc_power_up_cpu(unsigned int cpu) |
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{ |
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return rcar_sysc_power_cpu(cpu, true); |
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} |
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#endif /* CONFIG_ARCH_R8A7779 */
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