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739 lines
18 KiB
739 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2011-2017, The Linux Foundation |
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*/ |
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|
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#include <linux/irq.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/slab.h> |
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#include <linux/io.h> |
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#include <linux/interrupt.h> |
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#include <linux/platform_device.h> |
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#include <linux/delay.h> |
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#include <linux/clk.h> |
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#include <linux/of.h> |
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#include <linux/pm_runtime.h> |
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#include "slimbus.h" |
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|
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/* Manager registers */ |
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#define MGR_CFG 0x200 |
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#define MGR_STATUS 0x204 |
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#define MGR_INT_EN 0x210 |
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#define MGR_INT_STAT 0x214 |
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#define MGR_INT_CLR 0x218 |
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#define MGR_TX_MSG 0x230 |
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#define MGR_RX_MSG 0x270 |
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#define MGR_IE_STAT 0x2F0 |
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#define MGR_VE_STAT 0x300 |
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#define MGR_CFG_ENABLE 1 |
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/* Framer registers */ |
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#define FRM_CFG 0x400 |
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#define FRM_STAT 0x404 |
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#define FRM_INT_EN 0x410 |
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#define FRM_INT_STAT 0x414 |
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#define FRM_INT_CLR 0x418 |
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#define FRM_WAKEUP 0x41C |
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#define FRM_CLKCTL_DONE 0x420 |
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#define FRM_IE_STAT 0x430 |
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#define FRM_VE_STAT 0x440 |
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|
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/* Interface registers */ |
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#define INTF_CFG 0x600 |
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#define INTF_STAT 0x604 |
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#define INTF_INT_EN 0x610 |
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#define INTF_INT_STAT 0x614 |
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#define INTF_INT_CLR 0x618 |
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#define INTF_IE_STAT 0x630 |
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#define INTF_VE_STAT 0x640 |
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|
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/* Interrupt status bits */ |
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#define MGR_INT_TX_NACKED_2 BIT(25) |
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#define MGR_INT_MSG_BUF_CONTE BIT(26) |
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#define MGR_INT_RX_MSG_RCVD BIT(30) |
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#define MGR_INT_TX_MSG_SENT BIT(31) |
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/* Framer config register settings */ |
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#define FRM_ACTIVE 1 |
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#define CLK_GEAR 7 |
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#define ROOT_FREQ 11 |
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#define REF_CLK_GEAR 15 |
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#define INTR_WAKE 19 |
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#define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \ |
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((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16)) |
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|
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#define SLIM_ROOT_FREQ 24576000 |
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#define QCOM_SLIM_AUTOSUSPEND 1000 |
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/* MAX message size over control channel */ |
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#define SLIM_MSGQ_BUF_LEN 40 |
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#define QCOM_TX_MSGS 2 |
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#define QCOM_RX_MSGS 8 |
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#define QCOM_BUF_ALLOC_RETRIES 10 |
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#define CFG_PORT(r, v) ((v) ? CFG_PORT_V2(r) : CFG_PORT_V1(r)) |
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|
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/* V2 Component registers */ |
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#define CFG_PORT_V2(r) ((r ## _V2)) |
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#define COMP_CFG_V2 4 |
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#define COMP_TRUST_CFG_V2 0x3000 |
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|
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/* V1 Component registers */ |
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#define CFG_PORT_V1(r) ((r ## _V1)) |
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#define COMP_CFG_V1 0 |
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#define COMP_TRUST_CFG_V1 0x14 |
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/* Resource group info for manager, and non-ported generic device-components */ |
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#define EE_MGR_RSC_GRP (1 << 10) |
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#define EE_NGD_2 (2 << 6) |
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#define EE_NGD_1 0 |
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struct slim_ctrl_buf { |
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void *base; |
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spinlock_t lock; |
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int head; |
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int tail; |
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int sl_sz; |
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int n; |
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}; |
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struct qcom_slim_ctrl { |
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struct slim_controller ctrl; |
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struct slim_framer framer; |
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struct device *dev; |
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void __iomem *base; |
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void __iomem *slew_reg; |
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struct slim_ctrl_buf rx; |
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struct slim_ctrl_buf tx; |
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struct completion **wr_comp; |
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int irq; |
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struct workqueue_struct *rxwq; |
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struct work_struct wd; |
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struct clk *rclk; |
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struct clk *hclk; |
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}; |
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static void qcom_slim_queue_tx(struct qcom_slim_ctrl *ctrl, void *buf, |
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u8 len, u32 tx_reg) |
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{ |
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int count = (len + 3) >> 2; |
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__iowrite32_copy(ctrl->base + tx_reg, buf, count); |
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|
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/* Ensure Oder of subsequent writes */ |
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mb(); |
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} |
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static void *slim_alloc_rxbuf(struct qcom_slim_ctrl *ctrl) |
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{ |
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unsigned long flags; |
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int idx; |
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|
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spin_lock_irqsave(&ctrl->rx.lock, flags); |
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if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) { |
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spin_unlock_irqrestore(&ctrl->rx.lock, flags); |
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dev_err(ctrl->dev, "RX QUEUE full!"); |
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return NULL; |
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} |
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idx = ctrl->rx.tail; |
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ctrl->rx.tail = (ctrl->rx.tail + 1) % ctrl->rx.n; |
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spin_unlock_irqrestore(&ctrl->rx.lock, flags); |
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|
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return ctrl->rx.base + (idx * ctrl->rx.sl_sz); |
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} |
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static void slim_ack_txn(struct qcom_slim_ctrl *ctrl, int err) |
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{ |
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struct completion *comp; |
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unsigned long flags; |
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int idx; |
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|
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spin_lock_irqsave(&ctrl->tx.lock, flags); |
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idx = ctrl->tx.head; |
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ctrl->tx.head = (ctrl->tx.head + 1) % ctrl->tx.n; |
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spin_unlock_irqrestore(&ctrl->tx.lock, flags); |
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comp = ctrl->wr_comp[idx]; |
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ctrl->wr_comp[idx] = NULL; |
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complete(comp); |
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} |
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static irqreturn_t qcom_slim_handle_tx_irq(struct qcom_slim_ctrl *ctrl, |
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u32 stat) |
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{ |
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int err = 0; |
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if (stat & MGR_INT_TX_MSG_SENT) |
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writel_relaxed(MGR_INT_TX_MSG_SENT, |
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ctrl->base + MGR_INT_CLR); |
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|
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if (stat & MGR_INT_TX_NACKED_2) { |
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u32 mgr_stat = readl_relaxed(ctrl->base + MGR_STATUS); |
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u32 mgr_ie_stat = readl_relaxed(ctrl->base + MGR_IE_STAT); |
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u32 frm_stat = readl_relaxed(ctrl->base + FRM_STAT); |
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u32 frm_cfg = readl_relaxed(ctrl->base + FRM_CFG); |
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u32 frm_intr_stat = readl_relaxed(ctrl->base + FRM_INT_STAT); |
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u32 frm_ie_stat = readl_relaxed(ctrl->base + FRM_IE_STAT); |
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u32 intf_stat = readl_relaxed(ctrl->base + INTF_STAT); |
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u32 intf_intr_stat = readl_relaxed(ctrl->base + INTF_INT_STAT); |
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u32 intf_ie_stat = readl_relaxed(ctrl->base + INTF_IE_STAT); |
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writel_relaxed(MGR_INT_TX_NACKED_2, ctrl->base + MGR_INT_CLR); |
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dev_err(ctrl->dev, "TX Nack MGR:int:0x%x, stat:0x%x\n", |
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stat, mgr_stat); |
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dev_err(ctrl->dev, "TX Nack MGR:ie:0x%x\n", mgr_ie_stat); |
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dev_err(ctrl->dev, "TX Nack FRM:int:0x%x, stat:0x%x\n", |
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frm_intr_stat, frm_stat); |
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dev_err(ctrl->dev, "TX Nack FRM:cfg:0x%x, ie:0x%x\n", |
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frm_cfg, frm_ie_stat); |
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dev_err(ctrl->dev, "TX Nack INTF:intr:0x%x, stat:0x%x\n", |
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intf_intr_stat, intf_stat); |
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dev_err(ctrl->dev, "TX Nack INTF:ie:0x%x\n", |
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intf_ie_stat); |
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err = -ENOTCONN; |
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} |
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slim_ack_txn(ctrl, err); |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t qcom_slim_handle_rx_irq(struct qcom_slim_ctrl *ctrl, |
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u32 stat) |
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{ |
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u32 *rx_buf, pkt[10]; |
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bool q_rx = false; |
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u8 mc, mt, len; |
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pkt[0] = readl_relaxed(ctrl->base + MGR_RX_MSG); |
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mt = SLIM_HEADER_GET_MT(pkt[0]); |
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len = SLIM_HEADER_GET_RL(pkt[0]); |
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mc = SLIM_HEADER_GET_MC(pkt[0]>>8); |
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|
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/* |
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* this message cannot be handled by ISR, so |
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* let work-queue handle it |
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*/ |
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if (mt == SLIM_MSG_MT_CORE && mc == SLIM_MSG_MC_REPORT_PRESENT) { |
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rx_buf = (u32 *)slim_alloc_rxbuf(ctrl); |
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if (!rx_buf) { |
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dev_err(ctrl->dev, "dropping RX:0x%x due to RX full\n", |
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pkt[0]); |
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goto rx_ret_irq; |
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} |
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rx_buf[0] = pkt[0]; |
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} else { |
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rx_buf = pkt; |
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} |
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__ioread32_copy(rx_buf + 1, ctrl->base + MGR_RX_MSG + 4, |
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DIV_ROUND_UP(len, 4)); |
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switch (mc) { |
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case SLIM_MSG_MC_REPORT_PRESENT: |
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q_rx = true; |
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break; |
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case SLIM_MSG_MC_REPLY_INFORMATION: |
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case SLIM_MSG_MC_REPLY_VALUE: |
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slim_msg_response(&ctrl->ctrl, (u8 *)(rx_buf + 1), |
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(u8)(*rx_buf >> 24), (len - 4)); |
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break; |
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default: |
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dev_err(ctrl->dev, "unsupported MC,%x MT:%x\n", |
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mc, mt); |
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break; |
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} |
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rx_ret_irq: |
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writel(MGR_INT_RX_MSG_RCVD, ctrl->base + |
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MGR_INT_CLR); |
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if (q_rx) |
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queue_work(ctrl->rxwq, &ctrl->wd); |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t qcom_slim_interrupt(int irq, void *d) |
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{ |
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struct qcom_slim_ctrl *ctrl = d; |
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u32 stat = readl_relaxed(ctrl->base + MGR_INT_STAT); |
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int ret = IRQ_NONE; |
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if (stat & MGR_INT_TX_MSG_SENT || stat & MGR_INT_TX_NACKED_2) |
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ret = qcom_slim_handle_tx_irq(ctrl, stat); |
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if (stat & MGR_INT_RX_MSG_RCVD) |
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ret = qcom_slim_handle_rx_irq(ctrl, stat); |
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return ret; |
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} |
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static int qcom_clk_pause_wakeup(struct slim_controller *sctrl) |
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{ |
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struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev); |
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clk_prepare_enable(ctrl->hclk); |
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clk_prepare_enable(ctrl->rclk); |
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enable_irq(ctrl->irq); |
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writel_relaxed(1, ctrl->base + FRM_WAKEUP); |
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/* Make sure framer wakeup write goes through before ISR fires */ |
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mb(); |
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/* |
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* HW Workaround: Currently, slave is reporting lost-sync messages |
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* after SLIMbus comes out of clock pause. |
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* Transaction with slave fail before slave reports that message |
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* Give some time for that report to come |
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* SLIMbus wakes up in clock gear 10 at 24.576MHz. With each superframe |
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* being 250 usecs, we wait for 5-10 superframes here to ensure |
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* we get the message |
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*/ |
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usleep_range(1250, 2500); |
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return 0; |
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} |
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static void *slim_alloc_txbuf(struct qcom_slim_ctrl *ctrl, |
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struct slim_msg_txn *txn, |
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struct completion *done) |
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{ |
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unsigned long flags; |
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int idx; |
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spin_lock_irqsave(&ctrl->tx.lock, flags); |
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if (((ctrl->tx.head + 1) % ctrl->tx.n) == ctrl->tx.tail) { |
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spin_unlock_irqrestore(&ctrl->tx.lock, flags); |
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dev_err(ctrl->dev, "controller TX buf unavailable"); |
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return NULL; |
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} |
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idx = ctrl->tx.tail; |
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ctrl->wr_comp[idx] = done; |
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ctrl->tx.tail = (ctrl->tx.tail + 1) % ctrl->tx.n; |
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spin_unlock_irqrestore(&ctrl->tx.lock, flags); |
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return ctrl->tx.base + (idx * ctrl->tx.sl_sz); |
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} |
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static int qcom_xfer_msg(struct slim_controller *sctrl, |
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struct slim_msg_txn *txn) |
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{ |
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struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev); |
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DECLARE_COMPLETION_ONSTACK(done); |
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void *pbuf = slim_alloc_txbuf(ctrl, txn, &done); |
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unsigned long ms = txn->rl + HZ; |
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u8 *puc; |
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int ret = 0, timeout, retries = QCOM_BUF_ALLOC_RETRIES; |
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u8 la = txn->la; |
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u32 *head; |
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/* HW expects length field to be excluded */ |
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txn->rl--; |
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|
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/* spin till buffer is made available */ |
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if (!pbuf) { |
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while (retries--) { |
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usleep_range(10000, 15000); |
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pbuf = slim_alloc_txbuf(ctrl, txn, &done); |
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if (pbuf) |
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break; |
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} |
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} |
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if (retries < 0 && !pbuf) |
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return -ENOMEM; |
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puc = (u8 *)pbuf; |
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head = (u32 *)pbuf; |
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if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) { |
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*head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, |
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txn->mc, 0, la); |
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puc += 3; |
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} else { |
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*head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, |
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txn->mc, 1, la); |
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puc += 2; |
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} |
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if (slim_tid_txn(txn->mt, txn->mc)) |
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*(puc++) = txn->tid; |
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if (slim_ec_txn(txn->mt, txn->mc)) { |
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*(puc++) = (txn->ec & 0xFF); |
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*(puc++) = (txn->ec >> 8) & 0xFF; |
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} |
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if (txn->msg && txn->msg->wbuf) |
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memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes); |
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qcom_slim_queue_tx(ctrl, head, txn->rl, MGR_TX_MSG); |
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timeout = wait_for_completion_timeout(&done, msecs_to_jiffies(ms)); |
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|
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if (!timeout) { |
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dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc, |
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txn->mt); |
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ret = -ETIMEDOUT; |
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} |
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return ret; |
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} |
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static int qcom_set_laddr(struct slim_controller *sctrl, |
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struct slim_eaddr *ead, u8 laddr) |
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{ |
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struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev); |
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struct { |
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__be16 manf_id; |
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__be16 prod_code; |
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u8 dev_index; |
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u8 instance; |
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u8 laddr; |
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} __packed p; |
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struct slim_val_inf msg = {0}; |
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DEFINE_SLIM_EDEST_TXN(txn, SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS, |
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10, laddr, &msg); |
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int ret; |
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p.manf_id = cpu_to_be16(ead->manf_id); |
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p.prod_code = cpu_to_be16(ead->prod_code); |
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p.dev_index = ead->dev_index; |
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p.instance = ead->instance; |
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p.laddr = laddr; |
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|
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msg.wbuf = (void *)&p; |
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msg.num_bytes = 7; |
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ret = slim_do_transfer(&ctrl->ctrl, &txn); |
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|
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if (ret) |
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dev_err(ctrl->dev, "set LA:0x%x failed:ret:%d\n", |
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laddr, ret); |
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return ret; |
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} |
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static int slim_get_current_rxbuf(struct qcom_slim_ctrl *ctrl, void *buf) |
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{ |
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unsigned long flags; |
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|
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spin_lock_irqsave(&ctrl->rx.lock, flags); |
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if (ctrl->rx.tail == ctrl->rx.head) { |
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spin_unlock_irqrestore(&ctrl->rx.lock, flags); |
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return -ENODATA; |
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} |
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memcpy(buf, ctrl->rx.base + (ctrl->rx.head * ctrl->rx.sl_sz), |
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ctrl->rx.sl_sz); |
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|
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ctrl->rx.head = (ctrl->rx.head + 1) % ctrl->rx.n; |
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spin_unlock_irqrestore(&ctrl->rx.lock, flags); |
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|
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return 0; |
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} |
|
|
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static void qcom_slim_rxwq(struct work_struct *work) |
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{ |
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u8 buf[SLIM_MSGQ_BUF_LEN]; |
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u8 mc, mt; |
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int ret; |
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struct qcom_slim_ctrl *ctrl = container_of(work, struct qcom_slim_ctrl, |
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wd); |
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|
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while ((slim_get_current_rxbuf(ctrl, buf)) != -ENODATA) { |
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mt = SLIM_HEADER_GET_MT(buf[0]); |
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mc = SLIM_HEADER_GET_MC(buf[1]); |
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if (mt == SLIM_MSG_MT_CORE && |
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mc == SLIM_MSG_MC_REPORT_PRESENT) { |
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struct slim_eaddr ea; |
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u8 laddr; |
|
|
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ea.manf_id = be16_to_cpup((__be16 *)&buf[2]); |
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ea.prod_code = be16_to_cpup((__be16 *)&buf[4]); |
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ea.dev_index = buf[6]; |
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ea.instance = buf[7]; |
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|
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ret = slim_device_report_present(&ctrl->ctrl, &ea, |
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&laddr); |
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if (ret < 0) |
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dev_err(ctrl->dev, "assign laddr failed:%d\n", |
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ret); |
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} else { |
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dev_err(ctrl->dev, "unexpected message:mc:%x, mt:%x\n", |
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mc, mt); |
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} |
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} |
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} |
|
|
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static void qcom_slim_prg_slew(struct platform_device *pdev, |
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struct qcom_slim_ctrl *ctrl) |
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{ |
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if (!ctrl->slew_reg) { |
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/* SLEW RATE register for this SLIMbus */ |
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ctrl->slew_reg = devm_platform_ioremap_resource_byname(pdev, "slew"); |
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if (IS_ERR(ctrl->slew_reg)) |
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return; |
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} |
|
|
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writel_relaxed(1, ctrl->slew_reg); |
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/* Make sure SLIMbus-slew rate enabling goes through */ |
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wmb(); |
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} |
|
|
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static int qcom_slim_probe(struct platform_device *pdev) |
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{ |
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struct qcom_slim_ctrl *ctrl; |
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struct slim_controller *sctrl; |
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struct resource *slim_mem; |
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int ret, ver; |
|
|
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ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL); |
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if (!ctrl) |
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return -ENOMEM; |
|
|
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ctrl->hclk = devm_clk_get(&pdev->dev, "iface"); |
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if (IS_ERR(ctrl->hclk)) |
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return PTR_ERR(ctrl->hclk); |
|
|
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ctrl->rclk = devm_clk_get(&pdev->dev, "core"); |
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if (IS_ERR(ctrl->rclk)) |
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return PTR_ERR(ctrl->rclk); |
|
|
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ret = clk_set_rate(ctrl->rclk, SLIM_ROOT_FREQ); |
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if (ret) { |
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dev_err(&pdev->dev, "ref-clock set-rate failed:%d\n", ret); |
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return ret; |
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} |
|
|
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ctrl->irq = platform_get_irq(pdev, 0); |
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if (!ctrl->irq) { |
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dev_err(&pdev->dev, "no slimbus IRQ\n"); |
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return -ENODEV; |
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} |
|
|
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sctrl = &ctrl->ctrl; |
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sctrl->dev = &pdev->dev; |
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ctrl->dev = &pdev->dev; |
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platform_set_drvdata(pdev, ctrl); |
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dev_set_drvdata(ctrl->dev, ctrl); |
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|
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slim_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); |
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ctrl->base = devm_ioremap_resource(ctrl->dev, slim_mem); |
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if (IS_ERR(ctrl->base)) |
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return PTR_ERR(ctrl->base); |
|
|
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sctrl->set_laddr = qcom_set_laddr; |
|
sctrl->xfer_msg = qcom_xfer_msg; |
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sctrl->wakeup = qcom_clk_pause_wakeup; |
|
ctrl->tx.n = QCOM_TX_MSGS; |
|
ctrl->tx.sl_sz = SLIM_MSGQ_BUF_LEN; |
|
ctrl->rx.n = QCOM_RX_MSGS; |
|
ctrl->rx.sl_sz = SLIM_MSGQ_BUF_LEN; |
|
ctrl->wr_comp = kcalloc(QCOM_TX_MSGS, sizeof(struct completion *), |
|
GFP_KERNEL); |
|
if (!ctrl->wr_comp) |
|
return -ENOMEM; |
|
|
|
spin_lock_init(&ctrl->rx.lock); |
|
spin_lock_init(&ctrl->tx.lock); |
|
INIT_WORK(&ctrl->wd, qcom_slim_rxwq); |
|
ctrl->rxwq = create_singlethread_workqueue("qcom_slim_rx"); |
|
if (!ctrl->rxwq) { |
|
dev_err(ctrl->dev, "Failed to start Rx WQ\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
ctrl->framer.rootfreq = SLIM_ROOT_FREQ / 8; |
|
ctrl->framer.superfreq = |
|
ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8; |
|
sctrl->a_framer = &ctrl->framer; |
|
sctrl->clkgear = SLIM_MAX_CLK_GEAR; |
|
|
|
qcom_slim_prg_slew(pdev, ctrl); |
|
|
|
ret = devm_request_irq(&pdev->dev, ctrl->irq, qcom_slim_interrupt, |
|
IRQF_TRIGGER_HIGH, "qcom_slim_irq", ctrl); |
|
if (ret) { |
|
dev_err(&pdev->dev, "request IRQ failed\n"); |
|
goto err_request_irq_failed; |
|
} |
|
|
|
ret = clk_prepare_enable(ctrl->hclk); |
|
if (ret) |
|
goto err_hclk_enable_failed; |
|
|
|
ret = clk_prepare_enable(ctrl->rclk); |
|
if (ret) |
|
goto err_rclk_enable_failed; |
|
|
|
ctrl->tx.base = devm_kcalloc(&pdev->dev, ctrl->tx.n, ctrl->tx.sl_sz, |
|
GFP_KERNEL); |
|
if (!ctrl->tx.base) { |
|
ret = -ENOMEM; |
|
goto err; |
|
} |
|
|
|
ctrl->rx.base = devm_kcalloc(&pdev->dev,ctrl->rx.n, ctrl->rx.sl_sz, |
|
GFP_KERNEL); |
|
if (!ctrl->rx.base) { |
|
ret = -ENOMEM; |
|
goto err; |
|
} |
|
|
|
/* Register with framework before enabling frame, clock */ |
|
ret = slim_register_controller(&ctrl->ctrl); |
|
if (ret) { |
|
dev_err(ctrl->dev, "error adding controller\n"); |
|
goto err; |
|
} |
|
|
|
ver = readl_relaxed(ctrl->base); |
|
/* Version info in 16 MSbits */ |
|
ver >>= 16; |
|
/* Component register initialization */ |
|
writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver)); |
|
writel((EE_MGR_RSC_GRP | EE_NGD_2 | EE_NGD_1), |
|
ctrl->base + CFG_PORT(COMP_TRUST_CFG, ver)); |
|
|
|
writel((MGR_INT_TX_NACKED_2 | |
|
MGR_INT_MSG_BUF_CONTE | MGR_INT_RX_MSG_RCVD | |
|
MGR_INT_TX_MSG_SENT), ctrl->base + MGR_INT_EN); |
|
writel(1, ctrl->base + MGR_CFG); |
|
/* Framer register initialization */ |
|
writel((1 << INTR_WAKE) | (0xA << REF_CLK_GEAR) | |
|
(0xA << CLK_GEAR) | (1 << ROOT_FREQ) | (1 << FRM_ACTIVE) | 1, |
|
ctrl->base + FRM_CFG); |
|
writel(MGR_CFG_ENABLE, ctrl->base + MGR_CFG); |
|
writel(1, ctrl->base + INTF_CFG); |
|
writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver)); |
|
|
|
pm_runtime_use_autosuspend(&pdev->dev); |
|
pm_runtime_set_autosuspend_delay(&pdev->dev, QCOM_SLIM_AUTOSUSPEND); |
|
pm_runtime_set_active(&pdev->dev); |
|
pm_runtime_mark_last_busy(&pdev->dev); |
|
pm_runtime_enable(&pdev->dev); |
|
|
|
dev_dbg(ctrl->dev, "QCOM SB controller is up:ver:0x%x!\n", ver); |
|
return 0; |
|
|
|
err: |
|
clk_disable_unprepare(ctrl->rclk); |
|
err_rclk_enable_failed: |
|
clk_disable_unprepare(ctrl->hclk); |
|
err_hclk_enable_failed: |
|
err_request_irq_failed: |
|
destroy_workqueue(ctrl->rxwq); |
|
return ret; |
|
} |
|
|
|
static int qcom_slim_remove(struct platform_device *pdev) |
|
{ |
|
struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev); |
|
|
|
pm_runtime_disable(&pdev->dev); |
|
slim_unregister_controller(&ctrl->ctrl); |
|
clk_disable_unprepare(ctrl->rclk); |
|
clk_disable_unprepare(ctrl->hclk); |
|
destroy_workqueue(ctrl->rxwq); |
|
return 0; |
|
} |
|
|
|
/* |
|
* If PM_RUNTIME is not defined, these 2 functions become helper |
|
* functions to be called from system suspend/resume. |
|
*/ |
|
#ifdef CONFIG_PM |
|
static int qcom_slim_runtime_suspend(struct device *device) |
|
{ |
|
struct qcom_slim_ctrl *ctrl = dev_get_drvdata(device); |
|
int ret; |
|
|
|
dev_dbg(device, "pm_runtime: suspending...\n"); |
|
ret = slim_ctrl_clk_pause(&ctrl->ctrl, false, SLIM_CLK_UNSPECIFIED); |
|
if (ret) { |
|
dev_err(device, "clk pause not entered:%d", ret); |
|
} else { |
|
disable_irq(ctrl->irq); |
|
clk_disable_unprepare(ctrl->hclk); |
|
clk_disable_unprepare(ctrl->rclk); |
|
} |
|
return ret; |
|
} |
|
|
|
static int qcom_slim_runtime_resume(struct device *device) |
|
{ |
|
struct qcom_slim_ctrl *ctrl = dev_get_drvdata(device); |
|
int ret = 0; |
|
|
|
dev_dbg(device, "pm_runtime: resuming...\n"); |
|
ret = slim_ctrl_clk_pause(&ctrl->ctrl, true, 0); |
|
if (ret) |
|
dev_err(device, "clk pause not exited:%d", ret); |
|
return ret; |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int qcom_slim_suspend(struct device *dev) |
|
{ |
|
int ret = 0; |
|
|
|
if (!pm_runtime_enabled(dev) || |
|
(!pm_runtime_suspended(dev))) { |
|
dev_dbg(dev, "system suspend"); |
|
ret = qcom_slim_runtime_suspend(dev); |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static int qcom_slim_resume(struct device *dev) |
|
{ |
|
if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { |
|
int ret; |
|
|
|
dev_dbg(dev, "system resume"); |
|
ret = qcom_slim_runtime_resume(dev); |
|
if (!ret) { |
|
pm_runtime_mark_last_busy(dev); |
|
pm_request_autosuspend(dev); |
|
} |
|
return ret; |
|
|
|
} |
|
return 0; |
|
} |
|
#endif /* CONFIG_PM_SLEEP */ |
|
|
|
static const struct dev_pm_ops qcom_slim_dev_pm_ops = { |
|
SET_SYSTEM_SLEEP_PM_OPS(qcom_slim_suspend, qcom_slim_resume) |
|
SET_RUNTIME_PM_OPS( |
|
qcom_slim_runtime_suspend, |
|
qcom_slim_runtime_resume, |
|
NULL |
|
) |
|
}; |
|
|
|
static const struct of_device_id qcom_slim_dt_match[] = { |
|
{ .compatible = "qcom,slim", }, |
|
{ .compatible = "qcom,apq8064-slim", }, |
|
{} |
|
}; |
|
|
|
static struct platform_driver qcom_slim_driver = { |
|
.probe = qcom_slim_probe, |
|
.remove = qcom_slim_remove, |
|
.driver = { |
|
.name = "qcom_slim_ctrl", |
|
.of_match_table = qcom_slim_dt_match, |
|
.pm = &qcom_slim_dev_pm_ops, |
|
}, |
|
}; |
|
module_platform_driver(qcom_slim_driver); |
|
|
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_DESCRIPTION("Qualcomm SLIMbus Controller");
|
|
|