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573 lines
14 KiB
573 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
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*/ |
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#include <linux/of.h> |
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/rtc.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm.h> |
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#include <linux/regmap.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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/* RTC Register offsets from RTC CTRL REG */ |
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#define PM8XXX_ALARM_CTRL_OFFSET 0x01 |
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#define PM8XXX_RTC_WRITE_OFFSET 0x02 |
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#define PM8XXX_RTC_READ_OFFSET 0x06 |
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#define PM8XXX_ALARM_RW_OFFSET 0x0A |
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/* RTC_CTRL register bit fields */ |
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#define PM8xxx_RTC_ENABLE BIT(7) |
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#define PM8xxx_RTC_ALARM_CLEAR BIT(0) |
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#define PM8xxx_RTC_ALARM_ENABLE BIT(7) |
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#define NUM_8_BIT_RTC_REGS 0x4 |
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/** |
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* struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions |
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* @ctrl: base address of control register |
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* @write: base address of write register |
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* @read: base address of read register |
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* @alarm_ctrl: base address of alarm control register |
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* @alarm_ctrl2: base address of alarm control2 register |
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* @alarm_rw: base address of alarm read-write register |
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* @alarm_en: alarm enable mask |
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*/ |
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struct pm8xxx_rtc_regs { |
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unsigned int ctrl; |
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unsigned int write; |
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unsigned int read; |
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unsigned int alarm_ctrl; |
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unsigned int alarm_ctrl2; |
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unsigned int alarm_rw; |
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unsigned int alarm_en; |
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}; |
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/** |
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* struct pm8xxx_rtc - rtc driver internal structure |
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* @rtc: rtc device for this driver. |
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* @regmap: regmap used to access RTC registers |
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* @allow_set_time: indicates whether writing to the RTC is allowed |
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* @rtc_alarm_irq: rtc alarm irq number. |
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* @regs: rtc registers description. |
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* @rtc_dev: device structure. |
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* @ctrl_reg_lock: spinlock protecting access to ctrl_reg. |
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*/ |
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struct pm8xxx_rtc { |
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struct rtc_device *rtc; |
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struct regmap *regmap; |
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bool allow_set_time; |
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int rtc_alarm_irq; |
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const struct pm8xxx_rtc_regs *regs; |
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struct device *rtc_dev; |
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spinlock_t ctrl_reg_lock; |
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}; |
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/* |
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* Steps to write the RTC registers. |
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* 1. Disable alarm if enabled. |
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* 2. Disable rtc if enabled. |
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* 3. Write 0x00 to LSB. |
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* 4. Write Byte[1], Byte[2], Byte[3] then Byte[0]. |
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* 5. Enable rtc if disabled in step 2. |
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* 6. Enable alarm if disabled in step 1. |
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*/ |
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static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm) |
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{ |
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int rc, i; |
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unsigned long secs, irq_flags; |
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u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0; |
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unsigned int ctrl_reg, rtc_ctrl_reg; |
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
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if (!rtc_dd->allow_set_time) |
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return -EACCES; |
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secs = rtc_tm_to_time64(tm); |
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dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs); |
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for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) { |
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value[i] = secs & 0xFF; |
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secs >>= 8; |
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} |
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spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); |
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rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); |
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if (rc) |
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goto rtc_rw_fail; |
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if (ctrl_reg & regs->alarm_en) { |
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alarm_enabled = 1; |
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ctrl_reg &= ~regs->alarm_en; |
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rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); |
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if (rc) { |
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dev_err(dev, "Write to RTC Alarm control register failed\n"); |
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goto rtc_rw_fail; |
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} |
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} |
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/* Disable RTC H/w before writing on RTC register */ |
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rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg); |
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if (rc) |
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goto rtc_rw_fail; |
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if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) { |
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rtc_disabled = 1; |
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rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE; |
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rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg); |
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if (rc) { |
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dev_err(dev, "Write to RTC control register failed\n"); |
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goto rtc_rw_fail; |
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} |
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} |
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/* Write 0 to Byte[0] */ |
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rc = regmap_write(rtc_dd->regmap, regs->write, 0); |
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if (rc) { |
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dev_err(dev, "Write to RTC write data register failed\n"); |
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goto rtc_rw_fail; |
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} |
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/* Write Byte[1], Byte[2], Byte[3] */ |
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rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1, |
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&value[1], sizeof(value) - 1); |
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if (rc) { |
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dev_err(dev, "Write to RTC write data register failed\n"); |
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goto rtc_rw_fail; |
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} |
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/* Write Byte[0] */ |
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rc = regmap_write(rtc_dd->regmap, regs->write, value[0]); |
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if (rc) { |
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dev_err(dev, "Write to RTC write data register failed\n"); |
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goto rtc_rw_fail; |
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} |
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/* Enable RTC H/w after writing on RTC register */ |
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if (rtc_disabled) { |
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rtc_ctrl_reg |= PM8xxx_RTC_ENABLE; |
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rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg); |
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if (rc) { |
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dev_err(dev, "Write to RTC control register failed\n"); |
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goto rtc_rw_fail; |
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} |
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} |
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if (alarm_enabled) { |
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ctrl_reg |= regs->alarm_en; |
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rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); |
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if (rc) { |
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dev_err(dev, "Write to RTC Alarm control register failed\n"); |
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goto rtc_rw_fail; |
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} |
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} |
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rtc_rw_fail: |
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
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return rc; |
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} |
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static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm) |
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{ |
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int rc; |
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u8 value[NUM_8_BIT_RTC_REGS]; |
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unsigned long secs; |
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unsigned int reg; |
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
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rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value)); |
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if (rc) { |
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dev_err(dev, "RTC read data register failed\n"); |
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return rc; |
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} |
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/* |
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* Read the LSB again and check if there has been a carry over. |
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* If there is, redo the read operation. |
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*/ |
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rc = regmap_read(rtc_dd->regmap, regs->read, ®); |
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if (rc < 0) { |
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dev_err(dev, "RTC read data register failed\n"); |
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return rc; |
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} |
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if (unlikely(reg < value[0])) { |
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rc = regmap_bulk_read(rtc_dd->regmap, regs->read, |
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value, sizeof(value)); |
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if (rc) { |
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dev_err(dev, "RTC read data register failed\n"); |
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return rc; |
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} |
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} |
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secs = value[0] | (value[1] << 8) | (value[2] << 16) | |
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((unsigned long)value[3] << 24); |
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rtc_time64_to_tm(secs, tm); |
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dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm); |
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return 0; |
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} |
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static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
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{ |
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int rc, i; |
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u8 value[NUM_8_BIT_RTC_REGS]; |
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unsigned int ctrl_reg; |
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unsigned long secs, irq_flags; |
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
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secs = rtc_tm_to_time64(&alarm->time); |
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for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) { |
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value[i] = secs & 0xFF; |
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secs >>= 8; |
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} |
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spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); |
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rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value, |
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sizeof(value)); |
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if (rc) { |
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dev_err(dev, "Write to RTC ALARM register failed\n"); |
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goto rtc_rw_fail; |
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} |
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rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); |
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if (rc) |
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goto rtc_rw_fail; |
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if (alarm->enabled) |
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ctrl_reg |= regs->alarm_en; |
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else |
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ctrl_reg &= ~regs->alarm_en; |
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rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); |
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if (rc) { |
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dev_err(dev, "Write to RTC alarm control register failed\n"); |
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goto rtc_rw_fail; |
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} |
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dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n", |
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&alarm->time, &alarm->time); |
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rtc_rw_fail: |
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
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return rc; |
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} |
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static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
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{ |
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int rc; |
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unsigned int ctrl_reg; |
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u8 value[NUM_8_BIT_RTC_REGS]; |
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unsigned long secs; |
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
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rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value, |
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sizeof(value)); |
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if (rc) { |
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dev_err(dev, "RTC alarm time read failed\n"); |
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return rc; |
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} |
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secs = value[0] | (value[1] << 8) | (value[2] << 16) | |
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((unsigned long)value[3] << 24); |
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rtc_time64_to_tm(secs, &alarm->time); |
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rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); |
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if (rc) { |
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dev_err(dev, "Read from RTC alarm control register failed\n"); |
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return rc; |
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} |
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alarm->enabled = !!(ctrl_reg & PM8xxx_RTC_ALARM_ENABLE); |
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dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n", |
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&alarm->time, &alarm->time); |
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return 0; |
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} |
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static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) |
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{ |
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int rc; |
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unsigned long irq_flags; |
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
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unsigned int ctrl_reg; |
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u8 value[NUM_8_BIT_RTC_REGS] = {0}; |
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spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); |
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rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); |
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if (rc) |
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goto rtc_rw_fail; |
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if (enable) |
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ctrl_reg |= regs->alarm_en; |
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else |
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ctrl_reg &= ~regs->alarm_en; |
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rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); |
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if (rc) { |
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dev_err(dev, "Write to RTC control register failed\n"); |
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goto rtc_rw_fail; |
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} |
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/* Clear Alarm register */ |
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if (!enable) { |
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rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value, |
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sizeof(value)); |
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if (rc) { |
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dev_err(dev, "Clear RTC ALARM register failed\n"); |
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goto rtc_rw_fail; |
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} |
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} |
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rtc_rw_fail: |
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
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return rc; |
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} |
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static const struct rtc_class_ops pm8xxx_rtc_ops = { |
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.read_time = pm8xxx_rtc_read_time, |
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.set_time = pm8xxx_rtc_set_time, |
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.set_alarm = pm8xxx_rtc_set_alarm, |
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.read_alarm = pm8xxx_rtc_read_alarm, |
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.alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable, |
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}; |
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static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id) |
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{ |
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struct pm8xxx_rtc *rtc_dd = dev_id; |
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
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unsigned int ctrl_reg; |
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int rc; |
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rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF); |
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spin_lock(&rtc_dd->ctrl_reg_lock); |
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/* Clear the alarm enable bit */ |
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rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); |
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if (rc) { |
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spin_unlock(&rtc_dd->ctrl_reg_lock); |
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goto rtc_alarm_handled; |
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} |
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ctrl_reg &= ~regs->alarm_en; |
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rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); |
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if (rc) { |
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spin_unlock(&rtc_dd->ctrl_reg_lock); |
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dev_err(rtc_dd->rtc_dev, |
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"Write to alarm control register failed\n"); |
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goto rtc_alarm_handled; |
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} |
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spin_unlock(&rtc_dd->ctrl_reg_lock); |
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/* Clear RTC alarm register */ |
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rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg); |
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if (rc) { |
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dev_err(rtc_dd->rtc_dev, |
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"RTC Alarm control2 register read failed\n"); |
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goto rtc_alarm_handled; |
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} |
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ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR; |
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rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg); |
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if (rc) |
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dev_err(rtc_dd->rtc_dev, |
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"Write to RTC Alarm control2 register failed\n"); |
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rtc_alarm_handled: |
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return IRQ_HANDLED; |
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} |
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static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd) |
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{ |
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
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unsigned int ctrl_reg; |
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int rc; |
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/* Check if the RTC is on, else turn it on */ |
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rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg); |
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if (rc) |
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return rc; |
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if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) { |
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ctrl_reg |= PM8xxx_RTC_ENABLE; |
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rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg); |
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if (rc) |
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return rc; |
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} |
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return 0; |
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} |
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static const struct pm8xxx_rtc_regs pm8921_regs = { |
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.ctrl = 0x11d, |
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.write = 0x11f, |
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.read = 0x123, |
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.alarm_rw = 0x127, |
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.alarm_ctrl = 0x11d, |
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.alarm_ctrl2 = 0x11e, |
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.alarm_en = BIT(1), |
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}; |
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static const struct pm8xxx_rtc_regs pm8058_regs = { |
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.ctrl = 0x1e8, |
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.write = 0x1ea, |
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.read = 0x1ee, |
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.alarm_rw = 0x1f2, |
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.alarm_ctrl = 0x1e8, |
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.alarm_ctrl2 = 0x1e9, |
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.alarm_en = BIT(1), |
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}; |
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static const struct pm8xxx_rtc_regs pm8941_regs = { |
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.ctrl = 0x6046, |
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.write = 0x6040, |
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.read = 0x6048, |
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.alarm_rw = 0x6140, |
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.alarm_ctrl = 0x6146, |
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.alarm_ctrl2 = 0x6148, |
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.alarm_en = BIT(7), |
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}; |
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static const struct pm8xxx_rtc_regs pmk8350_regs = { |
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.ctrl = 0x6146, |
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.write = 0x6140, |
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.read = 0x6148, |
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.alarm_rw = 0x6240, |
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.alarm_ctrl = 0x6246, |
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.alarm_ctrl2 = 0x6248, |
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.alarm_en = BIT(7), |
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}; |
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/* |
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* Hardcoded RTC bases until IORESOURCE_REG mapping is figured out |
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*/ |
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static const struct of_device_id pm8xxx_id_table[] = { |
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{ .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs }, |
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{ .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs }, |
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{ .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs }, |
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{ .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs }, |
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{ .compatible = "qcom,pmk8350-rtc", .data = &pmk8350_regs }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, pm8xxx_id_table); |
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static int pm8xxx_rtc_probe(struct platform_device *pdev) |
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{ |
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int rc; |
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struct pm8xxx_rtc *rtc_dd; |
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const struct of_device_id *match; |
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match = of_match_node(pm8xxx_id_table, pdev->dev.of_node); |
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if (!match) |
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return -ENXIO; |
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rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL); |
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if (rtc_dd == NULL) |
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return -ENOMEM; |
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/* Initialise spinlock to protect RTC control register */ |
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spin_lock_init(&rtc_dd->ctrl_reg_lock); |
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rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
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if (!rtc_dd->regmap) { |
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dev_err(&pdev->dev, "Parent regmap unavailable.\n"); |
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return -ENXIO; |
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} |
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rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0); |
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if (rtc_dd->rtc_alarm_irq < 0) |
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return -ENXIO; |
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rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node, |
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"allow-set-time"); |
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rtc_dd->regs = match->data; |
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rtc_dd->rtc_dev = &pdev->dev; |
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rc = pm8xxx_rtc_enable(rtc_dd); |
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if (rc) |
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return rc; |
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platform_set_drvdata(pdev, rtc_dd); |
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device_init_wakeup(&pdev->dev, 1); |
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/* Register the RTC device */ |
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rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev); |
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if (IS_ERR(rtc_dd->rtc)) |
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return PTR_ERR(rtc_dd->rtc); |
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rtc_dd->rtc->ops = &pm8xxx_rtc_ops; |
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rtc_dd->rtc->range_max = U32_MAX; |
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/* Request the alarm IRQ */ |
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rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq, |
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pm8xxx_alarm_trigger, |
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IRQF_TRIGGER_RISING, |
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"pm8xxx_rtc_alarm", rtc_dd); |
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if (rc < 0) { |
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dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc); |
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return rc; |
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} |
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return devm_rtc_register_device(rtc_dd->rtc); |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int pm8xxx_rtc_resume(struct device *dev) |
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{ |
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
|
|
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if (device_may_wakeup(dev)) |
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disable_irq_wake(rtc_dd->rtc_alarm_irq); |
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|
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return 0; |
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} |
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|
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static int pm8xxx_rtc_suspend(struct device *dev) |
|
{ |
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
|
|
|
if (device_may_wakeup(dev)) |
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enable_irq_wake(rtc_dd->rtc_alarm_irq); |
|
|
|
return 0; |
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} |
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#endif |
|
|
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static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops, |
|
pm8xxx_rtc_suspend, |
|
pm8xxx_rtc_resume); |
|
|
|
static struct platform_driver pm8xxx_rtc_driver = { |
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.probe = pm8xxx_rtc_probe, |
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.driver = { |
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.name = "rtc-pm8xxx", |
|
.pm = &pm8xxx_rtc_pm_ops, |
|
.of_match_table = pm8xxx_id_table, |
|
}, |
|
}; |
|
|
|
module_platform_driver(pm8xxx_rtc_driver); |
|
|
|
MODULE_ALIAS("platform:rtc-pm8xxx"); |
|
MODULE_DESCRIPTION("PMIC8xxx RTC driver"); |
|
MODULE_LICENSE("GPL v2"); |
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MODULE_AUTHOR("Anirudh Ghayal <[email protected]>");
|
|
|