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134 lines
3.2 KiB
134 lines
3.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2015, National Instruments Corp. |
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* |
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* Xilinx Zynq Reset controller driver |
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* |
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* Author: Moritz Fischer <[email protected]> |
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*/ |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/init.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/reset-controller.h> |
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#include <linux/regmap.h> |
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#include <linux/types.h> |
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struct zynq_reset_data { |
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struct regmap *slcr; |
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struct reset_controller_dev rcdev; |
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u32 offset; |
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}; |
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#define to_zynq_reset_data(p) \ |
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container_of((p), struct zynq_reset_data, rcdev) |
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static int zynq_reset_assert(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct zynq_reset_data *priv = to_zynq_reset_data(rcdev); |
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int bank = id / BITS_PER_LONG; |
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int offset = id % BITS_PER_LONG; |
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pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__, |
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bank, offset); |
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return regmap_update_bits(priv->slcr, |
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priv->offset + (bank * 4), |
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BIT(offset), |
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BIT(offset)); |
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} |
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static int zynq_reset_deassert(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct zynq_reset_data *priv = to_zynq_reset_data(rcdev); |
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int bank = id / BITS_PER_LONG; |
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int offset = id % BITS_PER_LONG; |
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pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__, |
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bank, offset); |
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return regmap_update_bits(priv->slcr, |
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priv->offset + (bank * 4), |
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BIT(offset), |
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~BIT(offset)); |
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} |
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static int zynq_reset_status(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct zynq_reset_data *priv = to_zynq_reset_data(rcdev); |
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int bank = id / BITS_PER_LONG; |
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int offset = id % BITS_PER_LONG; |
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int ret; |
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u32 reg; |
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pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__, |
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bank, offset); |
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ret = regmap_read(priv->slcr, priv->offset + (bank * 4), ®); |
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if (ret) |
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return ret; |
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return !!(reg & BIT(offset)); |
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} |
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static const struct reset_control_ops zynq_reset_ops = { |
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.assert = zynq_reset_assert, |
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.deassert = zynq_reset_deassert, |
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.status = zynq_reset_status, |
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}; |
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static int zynq_reset_probe(struct platform_device *pdev) |
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{ |
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struct resource *res; |
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struct zynq_reset_data *priv; |
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, priv); |
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priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
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"syscon"); |
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if (IS_ERR(priv->slcr)) { |
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dev_err(&pdev->dev, "unable to get zynq-slcr regmap"); |
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return PTR_ERR(priv->slcr); |
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} |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!res) { |
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dev_err(&pdev->dev, "missing IO resource\n"); |
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return -ENODEV; |
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} |
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priv->offset = res->start; |
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priv->rcdev.owner = THIS_MODULE; |
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priv->rcdev.nr_resets = resource_size(res) / 4 * BITS_PER_LONG; |
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priv->rcdev.ops = &zynq_reset_ops; |
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priv->rcdev.of_node = pdev->dev.of_node; |
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return devm_reset_controller_register(&pdev->dev, &priv->rcdev); |
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} |
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static const struct of_device_id zynq_reset_dt_ids[] = { |
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{ .compatible = "xlnx,zynq-reset", }, |
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{ /* sentinel */ }, |
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}; |
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static struct platform_driver zynq_reset_driver = { |
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.probe = zynq_reset_probe, |
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.driver = { |
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.name = KBUILD_MODNAME, |
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.of_match_table = zynq_reset_dt_ids, |
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}, |
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}; |
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builtin_platform_driver(zynq_reset_driver);
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