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846 lines
23 KiB
846 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander |
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* |
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* Copyright (C) 2019 STMicroelectronics |
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* Author(s): Amelie Delaunay <[email protected]>. |
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*/ |
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#include <linux/gpio/driver.h> |
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#include <linux/interrupt.h> |
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#include <linux/mfd/stmfx.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/pinctrl/pinconf.h> |
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#include <linux/pinctrl/pinmux.h> |
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#include "core.h" |
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#include "pinctrl-utils.h" |
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/* GPIOs expander */ |
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/* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */ |
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#define STMFX_REG_GPIO_STATE STMFX_REG_GPIO_STATE1 /* R */ |
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/* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */ |
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#define STMFX_REG_GPIO_DIR STMFX_REG_GPIO_DIR1 /* RW */ |
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/* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */ |
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#define STMFX_REG_GPIO_TYPE STMFX_REG_GPIO_TYPE1 /* RW */ |
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/* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */ |
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#define STMFX_REG_GPIO_PUPD STMFX_REG_GPIO_PUPD1 /* RW */ |
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/* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */ |
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#define STMFX_REG_GPO_SET STMFX_REG_GPO_SET1 /* RW */ |
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/* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */ |
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#define STMFX_REG_GPO_CLR STMFX_REG_GPO_CLR1 /* RW */ |
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/* IRQ_GPI_SRC1 0x48, IRQ_GPI_SRC2 0x49, IRQ_GPI_SRC3 0x4A */ |
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#define STMFX_REG_IRQ_GPI_SRC STMFX_REG_IRQ_GPI_SRC1 /* RW */ |
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/* IRQ_GPI_EVT1 0x4C, IRQ_GPI_EVT2 0x4D, IRQ_GPI_EVT3 0x4E */ |
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#define STMFX_REG_IRQ_GPI_EVT STMFX_REG_IRQ_GPI_EVT1 /* RW */ |
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/* IRQ_GPI_TYPE1 0x50, IRQ_GPI_TYPE2 0x51, IRQ_GPI_TYPE3 0x52 */ |
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#define STMFX_REG_IRQ_GPI_TYPE STMFX_REG_IRQ_GPI_TYPE1 /* RW */ |
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/* IRQ_GPI_PENDING1 0x0C, IRQ_GPI_PENDING2 0x0D, IRQ_GPI_PENDING3 0x0E*/ |
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#define STMFX_REG_IRQ_GPI_PENDING STMFX_REG_IRQ_GPI_PENDING1 /* R */ |
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/* IRQ_GPI_ACK1 0x54, IRQ_GPI_ACK2 0x55, IRQ_GPI_ACK3 0x56 */ |
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#define STMFX_REG_IRQ_GPI_ACK STMFX_REG_IRQ_GPI_ACK1 /* RW */ |
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#define NR_GPIO_REGS 3 |
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#define NR_GPIOS_PER_REG 8 |
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#define get_reg(offset) ((offset) / NR_GPIOS_PER_REG) |
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#define get_shift(offset) ((offset) % NR_GPIOS_PER_REG) |
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#define get_mask(offset) (BIT(get_shift(offset))) |
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/* |
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* STMFX pinctrl can have up to 24 pins if STMFX other functions are not used. |
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* Pins availability is managed thanks to gpio-ranges property. |
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*/ |
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static const struct pinctrl_pin_desc stmfx_pins[] = { |
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PINCTRL_PIN(0, "gpio0"), |
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PINCTRL_PIN(1, "gpio1"), |
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PINCTRL_PIN(2, "gpio2"), |
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PINCTRL_PIN(3, "gpio3"), |
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PINCTRL_PIN(4, "gpio4"), |
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PINCTRL_PIN(5, "gpio5"), |
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PINCTRL_PIN(6, "gpio6"), |
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PINCTRL_PIN(7, "gpio7"), |
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PINCTRL_PIN(8, "gpio8"), |
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PINCTRL_PIN(9, "gpio9"), |
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PINCTRL_PIN(10, "gpio10"), |
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PINCTRL_PIN(11, "gpio11"), |
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PINCTRL_PIN(12, "gpio12"), |
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PINCTRL_PIN(13, "gpio13"), |
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PINCTRL_PIN(14, "gpio14"), |
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PINCTRL_PIN(15, "gpio15"), |
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PINCTRL_PIN(16, "agpio0"), |
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PINCTRL_PIN(17, "agpio1"), |
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PINCTRL_PIN(18, "agpio2"), |
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PINCTRL_PIN(19, "agpio3"), |
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PINCTRL_PIN(20, "agpio4"), |
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PINCTRL_PIN(21, "agpio5"), |
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PINCTRL_PIN(22, "agpio6"), |
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PINCTRL_PIN(23, "agpio7"), |
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}; |
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struct stmfx_pinctrl { |
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struct device *dev; |
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struct stmfx *stmfx; |
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struct pinctrl_dev *pctl_dev; |
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struct pinctrl_desc pctl_desc; |
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struct gpio_chip gpio_chip; |
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struct irq_chip irq_chip; |
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struct mutex lock; /* IRQ bus lock */ |
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unsigned long gpio_valid_mask; |
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/* Cache of IRQ_GPI_* registers for bus_lock */ |
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u8 irq_gpi_src[NR_GPIO_REGS]; |
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u8 irq_gpi_type[NR_GPIO_REGS]; |
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u8 irq_gpi_evt[NR_GPIO_REGS]; |
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u8 irq_toggle_edge[NR_GPIO_REGS]; |
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#ifdef CONFIG_PM |
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/* Backup of GPIO_* registers for suspend/resume */ |
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u8 bkp_gpio_state[NR_GPIO_REGS]; |
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u8 bkp_gpio_dir[NR_GPIO_REGS]; |
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u8 bkp_gpio_type[NR_GPIO_REGS]; |
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u8 bkp_gpio_pupd[NR_GPIO_REGS]; |
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#endif |
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}; |
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static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset) |
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{ |
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struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); |
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u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset); |
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u32 mask = get_mask(offset); |
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u32 value; |
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int ret; |
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ret = regmap_read(pctl->stmfx->map, reg, &value); |
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return ret ? ret : !!(value & mask); |
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} |
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static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) |
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{ |
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struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); |
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u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR; |
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u32 mask = get_mask(offset); |
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regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset), |
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mask, mask); |
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} |
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static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) |
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{ |
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struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); |
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u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); |
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u32 mask = get_mask(offset); |
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u32 val; |
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int ret; |
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ret = regmap_read(pctl->stmfx->map, reg, &val); |
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/* |
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* On stmfx, gpio pins direction is (0)input, (1)output. |
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*/ |
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if (ret) |
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return ret; |
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if (val & mask) |
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return GPIO_LINE_DIRECTION_OUT; |
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return GPIO_LINE_DIRECTION_IN; |
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} |
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static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) |
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{ |
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struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); |
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u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); |
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u32 mask = get_mask(offset); |
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return regmap_write_bits(pctl->stmfx->map, reg, mask, 0); |
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} |
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static int stmfx_gpio_direction_output(struct gpio_chip *gc, |
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unsigned int offset, int value) |
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{ |
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struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); |
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u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); |
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u32 mask = get_mask(offset); |
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stmfx_gpio_set(gc, offset, value); |
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return regmap_write_bits(pctl->stmfx->map, reg, mask, mask); |
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} |
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static int stmfx_pinconf_get_pupd(struct stmfx_pinctrl *pctl, |
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unsigned int offset) |
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{ |
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u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset); |
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u32 pupd, mask = get_mask(offset); |
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int ret; |
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ret = regmap_read(pctl->stmfx->map, reg, &pupd); |
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if (ret) |
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return ret; |
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return !!(pupd & mask); |
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} |
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static int stmfx_pinconf_set_pupd(struct stmfx_pinctrl *pctl, |
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unsigned int offset, u32 pupd) |
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{ |
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u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset); |
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u32 mask = get_mask(offset); |
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return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0); |
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} |
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static int stmfx_pinconf_get_type(struct stmfx_pinctrl *pctl, |
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unsigned int offset) |
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{ |
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u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset); |
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u32 type, mask = get_mask(offset); |
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int ret; |
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ret = regmap_read(pctl->stmfx->map, reg, &type); |
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if (ret) |
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return ret; |
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return !!(type & mask); |
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} |
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static int stmfx_pinconf_set_type(struct stmfx_pinctrl *pctl, |
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unsigned int offset, u32 type) |
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{ |
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u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset); |
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u32 mask = get_mask(offset); |
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return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0); |
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} |
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static int stmfx_pinconf_get(struct pinctrl_dev *pctldev, |
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unsigned int pin, unsigned long *config) |
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{ |
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struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
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u32 param = pinconf_to_config_param(*config); |
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struct pinctrl_gpio_range *range; |
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u32 arg = 0; |
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int ret, dir, type, pupd; |
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range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); |
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if (!range) |
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return -EINVAL; |
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dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin); |
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if (dir < 0) |
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return dir; |
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/* |
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* Currently the gpiolib IN is 1 and OUT is 0 but let's not count |
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* on it just to be on the safe side also in the future :) |
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*/ |
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dir = (dir == GPIO_LINE_DIRECTION_IN) ? 1 : 0; |
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type = stmfx_pinconf_get_type(pctl, pin); |
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if (type < 0) |
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return type; |
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pupd = stmfx_pinconf_get_pupd(pctl, pin); |
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if (pupd < 0) |
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return pupd; |
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switch (param) { |
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case PIN_CONFIG_BIAS_DISABLE: |
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if ((!dir && (!type || !pupd)) || (dir && !type)) |
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arg = 1; |
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break; |
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case PIN_CONFIG_BIAS_PULL_DOWN: |
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if (dir && type && !pupd) |
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arg = 1; |
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break; |
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case PIN_CONFIG_BIAS_PULL_UP: |
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if (type && pupd) |
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arg = 1; |
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break; |
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case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
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if ((!dir && type) || (dir && !type)) |
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arg = 1; |
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break; |
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case PIN_CONFIG_DRIVE_PUSH_PULL: |
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if ((!dir && !type) || (dir && type)) |
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arg = 1; |
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break; |
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case PIN_CONFIG_OUTPUT: |
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if (dir) |
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return -EINVAL; |
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ret = stmfx_gpio_get(&pctl->gpio_chip, pin); |
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if (ret < 0) |
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return ret; |
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arg = ret; |
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break; |
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default: |
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return -ENOTSUPP; |
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} |
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*config = pinconf_to_config_packed(param, arg); |
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return 0; |
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} |
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static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, |
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unsigned long *configs, unsigned int num_configs) |
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{ |
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struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
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struct pinctrl_gpio_range *range; |
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enum pin_config_param param; |
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u32 arg; |
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int i, ret; |
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range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); |
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if (!range) { |
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dev_err(pctldev->dev, "pin %d is not available\n", pin); |
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return -EINVAL; |
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} |
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for (i = 0; i < num_configs; i++) { |
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param = pinconf_to_config_param(configs[i]); |
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arg = pinconf_to_config_argument(configs[i]); |
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switch (param) { |
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case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: |
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case PIN_CONFIG_BIAS_DISABLE: |
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case PIN_CONFIG_DRIVE_PUSH_PULL: |
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ret = stmfx_pinconf_set_type(pctl, pin, 0); |
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if (ret) |
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return ret; |
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break; |
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case PIN_CONFIG_BIAS_PULL_DOWN: |
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ret = stmfx_pinconf_set_type(pctl, pin, 1); |
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if (ret) |
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return ret; |
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ret = stmfx_pinconf_set_pupd(pctl, pin, 0); |
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if (ret) |
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return ret; |
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break; |
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case PIN_CONFIG_BIAS_PULL_UP: |
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ret = stmfx_pinconf_set_type(pctl, pin, 1); |
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if (ret) |
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return ret; |
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ret = stmfx_pinconf_set_pupd(pctl, pin, 1); |
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if (ret) |
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return ret; |
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break; |
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case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
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ret = stmfx_pinconf_set_type(pctl, pin, 1); |
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if (ret) |
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return ret; |
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break; |
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case PIN_CONFIG_OUTPUT: |
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ret = stmfx_gpio_direction_output(&pctl->gpio_chip, |
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pin, arg); |
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if (ret) |
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return ret; |
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break; |
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default: |
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return -ENOTSUPP; |
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} |
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} |
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return 0; |
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} |
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static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev, |
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struct seq_file *s, unsigned int offset) |
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{ |
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struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
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struct pinctrl_gpio_range *range; |
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int dir, type, pupd, val; |
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range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, offset); |
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if (!range) |
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return; |
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dir = stmfx_gpio_get_direction(&pctl->gpio_chip, offset); |
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if (dir < 0) |
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return; |
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type = stmfx_pinconf_get_type(pctl, offset); |
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if (type < 0) |
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return; |
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pupd = stmfx_pinconf_get_pupd(pctl, offset); |
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if (pupd < 0) |
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return; |
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val = stmfx_gpio_get(&pctl->gpio_chip, offset); |
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if (val < 0) |
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return; |
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if (dir == GPIO_LINE_DIRECTION_OUT) { |
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seq_printf(s, "output %s ", val ? "high" : "low"); |
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if (type) |
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seq_printf(s, "open drain %s internal pull-up ", |
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pupd ? "with" : "without"); |
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else |
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seq_puts(s, "push pull no pull "); |
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} else { |
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seq_printf(s, "input %s ", val ? "high" : "low"); |
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if (type) |
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seq_printf(s, "with internal pull-%s ", |
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pupd ? "up" : "down"); |
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else |
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seq_printf(s, "%s ", pupd ? "floating" : "analog"); |
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} |
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} |
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static const struct pinconf_ops stmfx_pinconf_ops = { |
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.pin_config_get = stmfx_pinconf_get, |
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.pin_config_set = stmfx_pinconf_set, |
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.pin_config_dbg_show = stmfx_pinconf_dbg_show, |
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}; |
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static int stmfx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) |
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{ |
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return 0; |
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} |
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static const char *stmfx_pinctrl_get_group_name(struct pinctrl_dev *pctldev, |
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unsigned int selector) |
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{ |
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return NULL; |
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} |
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static int stmfx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, |
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unsigned int selector, |
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const unsigned int **pins, |
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unsigned int *num_pins) |
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{ |
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return -ENOTSUPP; |
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} |
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static const struct pinctrl_ops stmfx_pinctrl_ops = { |
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.get_groups_count = stmfx_pinctrl_get_groups_count, |
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.get_group_name = stmfx_pinctrl_get_group_name, |
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.get_group_pins = stmfx_pinctrl_get_group_pins, |
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.dt_node_to_map = pinconf_generic_dt_node_to_map_pin, |
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.dt_free_map = pinctrl_utils_free_map, |
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}; |
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static void stmfx_pinctrl_irq_mask(struct irq_data *data) |
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{ |
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struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); |
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struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); |
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u32 reg = get_reg(data->hwirq); |
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u32 mask = get_mask(data->hwirq); |
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pctl->irq_gpi_src[reg] &= ~mask; |
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} |
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static void stmfx_pinctrl_irq_unmask(struct irq_data *data) |
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{ |
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struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); |
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struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); |
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u32 reg = get_reg(data->hwirq); |
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u32 mask = get_mask(data->hwirq); |
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pctl->irq_gpi_src[reg] |= mask; |
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} |
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static int stmfx_pinctrl_irq_set_type(struct irq_data *data, unsigned int type) |
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{ |
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struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); |
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struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); |
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u32 reg = get_reg(data->hwirq); |
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u32 mask = get_mask(data->hwirq); |
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if (type == IRQ_TYPE_NONE) |
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return -EINVAL; |
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if (type & IRQ_TYPE_EDGE_BOTH) { |
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pctl->irq_gpi_evt[reg] |= mask; |
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irq_set_handler_locked(data, handle_edge_irq); |
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} else { |
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pctl->irq_gpi_evt[reg] &= ~mask; |
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irq_set_handler_locked(data, handle_level_irq); |
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} |
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if ((type & IRQ_TYPE_EDGE_RISING) || (type & IRQ_TYPE_LEVEL_HIGH)) |
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pctl->irq_gpi_type[reg] |= mask; |
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else |
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pctl->irq_gpi_type[reg] &= ~mask; |
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/* |
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* In case of (type & IRQ_TYPE_EDGE_BOTH), we need to know current |
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* GPIO value to set the right edge trigger. But in atomic context |
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* here we can't access registers over I2C. That's why (type & |
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* IRQ_TYPE_EDGE_BOTH) will be managed in .irq_sync_unlock. |
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*/ |
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if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) |
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pctl->irq_toggle_edge[reg] |= mask; |
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else |
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pctl->irq_toggle_edge[reg] &= mask; |
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return 0; |
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} |
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static void stmfx_pinctrl_irq_bus_lock(struct irq_data *data) |
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{ |
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struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); |
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struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); |
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mutex_lock(&pctl->lock); |
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} |
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static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data) |
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{ |
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struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); |
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struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); |
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u32 reg = get_reg(data->hwirq); |
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u32 mask = get_mask(data->hwirq); |
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/* |
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* In case of IRQ_TYPE_EDGE_BOTH), read the current GPIO value |
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* (this couldn't be done in .irq_set_type because of atomic context) |
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* to set the right irq trigger type. |
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*/ |
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if (pctl->irq_toggle_edge[reg] & mask) { |
|
if (stmfx_gpio_get(gpio_chip, data->hwirq)) |
|
pctl->irq_gpi_type[reg] &= ~mask; |
|
else |
|
pctl->irq_gpi_type[reg] |= mask; |
|
} |
|
|
|
regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT, |
|
pctl->irq_gpi_evt, NR_GPIO_REGS); |
|
regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE, |
|
pctl->irq_gpi_type, NR_GPIO_REGS); |
|
regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, |
|
pctl->irq_gpi_src, NR_GPIO_REGS); |
|
|
|
mutex_unlock(&pctl->lock); |
|
} |
|
|
|
static int stmfx_gpio_irq_request_resources(struct irq_data *data) |
|
{ |
|
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); |
|
int ret; |
|
|
|
ret = stmfx_gpio_direction_input(gpio_chip, data->hwirq); |
|
if (ret) |
|
return ret; |
|
|
|
return gpiochip_reqres_irq(gpio_chip, data->hwirq); |
|
} |
|
|
|
static void stmfx_gpio_irq_release_resources(struct irq_data *data) |
|
{ |
|
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); |
|
|
|
return gpiochip_relres_irq(gpio_chip, data->hwirq); |
|
} |
|
|
|
static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl, |
|
unsigned int offset) |
|
{ |
|
u32 reg = get_reg(offset); |
|
u32 mask = get_mask(offset); |
|
int val; |
|
|
|
if (!(pctl->irq_toggle_edge[reg] & mask)) |
|
return; |
|
|
|
val = stmfx_gpio_get(&pctl->gpio_chip, offset); |
|
if (val < 0) |
|
return; |
|
|
|
if (val) { |
|
pctl->irq_gpi_type[reg] &= mask; |
|
regmap_write_bits(pctl->stmfx->map, |
|
STMFX_REG_IRQ_GPI_TYPE + reg, |
|
mask, 0); |
|
|
|
} else { |
|
pctl->irq_gpi_type[reg] |= mask; |
|
regmap_write_bits(pctl->stmfx->map, |
|
STMFX_REG_IRQ_GPI_TYPE + reg, |
|
mask, mask); |
|
} |
|
} |
|
|
|
static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id) |
|
{ |
|
struct stmfx_pinctrl *pctl = (struct stmfx_pinctrl *)dev_id; |
|
struct gpio_chip *gc = &pctl->gpio_chip; |
|
u8 pending[NR_GPIO_REGS]; |
|
u8 src[NR_GPIO_REGS] = {0, 0, 0}; |
|
unsigned long n, status; |
|
int i, ret; |
|
|
|
ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING, |
|
&pending, NR_GPIO_REGS); |
|
if (ret) |
|
return IRQ_NONE; |
|
|
|
regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, |
|
src, NR_GPIO_REGS); |
|
|
|
BUILD_BUG_ON(NR_GPIO_REGS > sizeof(status)); |
|
for (i = 0, status = 0; i < NR_GPIO_REGS; i++) |
|
status |= (unsigned long)pending[i] << (i * 8); |
|
for_each_set_bit(n, &status, gc->ngpio) { |
|
handle_nested_irq(irq_find_mapping(gc->irq.domain, n)); |
|
stmfx_pinctrl_irq_toggle_trigger(pctl, n); |
|
} |
|
|
|
regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, |
|
pctl->irq_gpi_src, NR_GPIO_REGS); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl) |
|
{ |
|
struct pinctrl_gpio_range *gpio_range; |
|
struct pinctrl_dev *pctl_dev = pctl->pctl_dev; |
|
u32 func = STMFX_FUNC_GPIO; |
|
|
|
pctl->gpio_valid_mask = GENMASK(15, 0); |
|
|
|
gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 16); |
|
if (gpio_range) { |
|
func |= STMFX_FUNC_ALTGPIO_LOW; |
|
pctl->gpio_valid_mask |= GENMASK(19, 16); |
|
} |
|
|
|
gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 20); |
|
if (gpio_range) { |
|
func |= STMFX_FUNC_ALTGPIO_HIGH; |
|
pctl->gpio_valid_mask |= GENMASK(23, 20); |
|
} |
|
|
|
return stmfx_function_enable(pctl->stmfx, func); |
|
} |
|
|
|
static int stmfx_pinctrl_probe(struct platform_device *pdev) |
|
{ |
|
struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent); |
|
struct device_node *np = pdev->dev.of_node; |
|
struct stmfx_pinctrl *pctl; |
|
struct gpio_irq_chip *girq; |
|
int irq, ret; |
|
|
|
pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL); |
|
if (!pctl) |
|
return -ENOMEM; |
|
|
|
platform_set_drvdata(pdev, pctl); |
|
|
|
pctl->dev = &pdev->dev; |
|
pctl->stmfx = stmfx; |
|
|
|
if (!of_find_property(np, "gpio-ranges", NULL)) { |
|
dev_err(pctl->dev, "missing required gpio-ranges property\n"); |
|
return -EINVAL; |
|
} |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq <= 0) |
|
return -ENXIO; |
|
|
|
mutex_init(&pctl->lock); |
|
|
|
/* Register pin controller */ |
|
pctl->pctl_desc.name = "stmfx-pinctrl"; |
|
pctl->pctl_desc.pctlops = &stmfx_pinctrl_ops; |
|
pctl->pctl_desc.confops = &stmfx_pinconf_ops; |
|
pctl->pctl_desc.pins = stmfx_pins; |
|
pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins); |
|
pctl->pctl_desc.owner = THIS_MODULE; |
|
pctl->pctl_desc.link_consumers = true; |
|
|
|
ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc, |
|
pctl, &pctl->pctl_dev); |
|
if (ret) { |
|
dev_err(pctl->dev, "pinctrl registration failed\n"); |
|
return ret; |
|
} |
|
|
|
ret = pinctrl_enable(pctl->pctl_dev); |
|
if (ret) { |
|
dev_err(pctl->dev, "pinctrl enable failed\n"); |
|
return ret; |
|
} |
|
|
|
/* Register gpio controller */ |
|
pctl->gpio_chip.label = "stmfx-gpio"; |
|
pctl->gpio_chip.parent = pctl->dev; |
|
pctl->gpio_chip.get_direction = stmfx_gpio_get_direction; |
|
pctl->gpio_chip.direction_input = stmfx_gpio_direction_input; |
|
pctl->gpio_chip.direction_output = stmfx_gpio_direction_output; |
|
pctl->gpio_chip.get = stmfx_gpio_get; |
|
pctl->gpio_chip.set = stmfx_gpio_set; |
|
pctl->gpio_chip.set_config = gpiochip_generic_config; |
|
pctl->gpio_chip.base = -1; |
|
pctl->gpio_chip.ngpio = pctl->pctl_desc.npins; |
|
pctl->gpio_chip.can_sleep = true; |
|
pctl->gpio_chip.of_node = np; |
|
|
|
pctl->irq_chip.name = dev_name(pctl->dev); |
|
pctl->irq_chip.irq_mask = stmfx_pinctrl_irq_mask; |
|
pctl->irq_chip.irq_unmask = stmfx_pinctrl_irq_unmask; |
|
pctl->irq_chip.irq_set_type = stmfx_pinctrl_irq_set_type; |
|
pctl->irq_chip.irq_bus_lock = stmfx_pinctrl_irq_bus_lock; |
|
pctl->irq_chip.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock; |
|
pctl->irq_chip.irq_request_resources = stmfx_gpio_irq_request_resources; |
|
pctl->irq_chip.irq_release_resources = stmfx_gpio_irq_release_resources; |
|
|
|
girq = &pctl->gpio_chip.irq; |
|
girq->chip = &pctl->irq_chip; |
|
/* This will let us handle the parent IRQ in the driver */ |
|
girq->parent_handler = NULL; |
|
girq->num_parents = 0; |
|
girq->parents = NULL; |
|
girq->default_type = IRQ_TYPE_NONE; |
|
girq->handler = handle_bad_irq; |
|
girq->threaded = true; |
|
|
|
ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl); |
|
if (ret) { |
|
dev_err(pctl->dev, "gpio_chip registration failed\n"); |
|
return ret; |
|
} |
|
|
|
ret = stmfx_pinctrl_gpio_function_enable(pctl); |
|
if (ret) |
|
return ret; |
|
|
|
ret = devm_request_threaded_irq(pctl->dev, irq, NULL, |
|
stmfx_pinctrl_irq_thread_fn, |
|
IRQF_ONESHOT, |
|
pctl->irq_chip.name, pctl); |
|
if (ret) { |
|
dev_err(pctl->dev, "cannot request irq%d\n", irq); |
|
return ret; |
|
} |
|
|
|
dev_info(pctl->dev, |
|
"%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask)); |
|
|
|
return 0; |
|
} |
|
|
|
static int stmfx_pinctrl_remove(struct platform_device *pdev) |
|
{ |
|
struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent); |
|
|
|
return stmfx_function_disable(stmfx, |
|
STMFX_FUNC_GPIO | |
|
STMFX_FUNC_ALTGPIO_LOW | |
|
STMFX_FUNC_ALTGPIO_HIGH); |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int stmfx_pinctrl_backup_regs(struct stmfx_pinctrl *pctl) |
|
{ |
|
int ret; |
|
|
|
ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_STATE, |
|
&pctl->bkp_gpio_state, NR_GPIO_REGS); |
|
if (ret) |
|
return ret; |
|
ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_DIR, |
|
&pctl->bkp_gpio_dir, NR_GPIO_REGS); |
|
if (ret) |
|
return ret; |
|
ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_TYPE, |
|
&pctl->bkp_gpio_type, NR_GPIO_REGS); |
|
if (ret) |
|
return ret; |
|
ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_PUPD, |
|
&pctl->bkp_gpio_pupd, NR_GPIO_REGS); |
|
if (ret) |
|
return ret; |
|
|
|
return 0; |
|
} |
|
|
|
static int stmfx_pinctrl_restore_regs(struct stmfx_pinctrl *pctl) |
|
{ |
|
int ret; |
|
|
|
ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_DIR, |
|
pctl->bkp_gpio_dir, NR_GPIO_REGS); |
|
if (ret) |
|
return ret; |
|
ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_TYPE, |
|
pctl->bkp_gpio_type, NR_GPIO_REGS); |
|
if (ret) |
|
return ret; |
|
ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_PUPD, |
|
pctl->bkp_gpio_pupd, NR_GPIO_REGS); |
|
if (ret) |
|
return ret; |
|
ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPO_SET, |
|
pctl->bkp_gpio_state, NR_GPIO_REGS); |
|
if (ret) |
|
return ret; |
|
ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT, |
|
pctl->irq_gpi_evt, NR_GPIO_REGS); |
|
if (ret) |
|
return ret; |
|
ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE, |
|
pctl->irq_gpi_type, NR_GPIO_REGS); |
|
if (ret) |
|
return ret; |
|
ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, |
|
pctl->irq_gpi_src, NR_GPIO_REGS); |
|
if (ret) |
|
return ret; |
|
|
|
return 0; |
|
} |
|
|
|
static int stmfx_pinctrl_suspend(struct device *dev) |
|
{ |
|
struct stmfx_pinctrl *pctl = dev_get_drvdata(dev); |
|
int ret; |
|
|
|
ret = stmfx_pinctrl_backup_regs(pctl); |
|
if (ret) { |
|
dev_err(pctl->dev, "registers backup failure\n"); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int stmfx_pinctrl_resume(struct device *dev) |
|
{ |
|
struct stmfx_pinctrl *pctl = dev_get_drvdata(dev); |
|
int ret; |
|
|
|
ret = stmfx_pinctrl_restore_regs(pctl); |
|
if (ret) { |
|
dev_err(pctl->dev, "registers restoration failure\n"); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
static SIMPLE_DEV_PM_OPS(stmfx_pinctrl_dev_pm_ops, |
|
stmfx_pinctrl_suspend, stmfx_pinctrl_resume); |
|
|
|
static const struct of_device_id stmfx_pinctrl_of_match[] = { |
|
{ .compatible = "st,stmfx-0300-pinctrl", }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, stmfx_pinctrl_of_match); |
|
|
|
static struct platform_driver stmfx_pinctrl_driver = { |
|
.driver = { |
|
.name = "stmfx-pinctrl", |
|
.of_match_table = stmfx_pinctrl_of_match, |
|
.pm = &stmfx_pinctrl_dev_pm_ops, |
|
}, |
|
.probe = stmfx_pinctrl_probe, |
|
.remove = stmfx_pinctrl_remove, |
|
}; |
|
module_platform_driver(stmfx_pinctrl_driver); |
|
|
|
MODULE_DESCRIPTION("STMFX pinctrl/GPIO driver"); |
|
MODULE_AUTHOR("Amelie Delaunay <[email protected]>"); |
|
MODULE_LICENSE("GPL v2");
|
|
|