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466 lines
11 KiB
466 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* phy-uniphier-usb3hs.c - HS-PHY driver for Socionext UniPhier USB3 controller |
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* Copyright 2015-2018 Socionext Inc. |
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* Author: |
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* Kunihiko Hayashi <[email protected]> |
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* Contributors: |
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* Motoya Tanigawa <[email protected]> |
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* Masami Hiramatsu <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/nvmem-consumer.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/reset.h> |
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#include <linux/slab.h> |
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#define HSPHY_CFG0 0x0 |
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#define HSPHY_CFG0_HS_I_MASK GENMASK(31, 28) |
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#define HSPHY_CFG0_HSDISC_MASK GENMASK(27, 26) |
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#define HSPHY_CFG0_SWING_MASK GENMASK(17, 16) |
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#define HSPHY_CFG0_SEL_T_MASK GENMASK(15, 12) |
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#define HSPHY_CFG0_RTERM_MASK GENMASK(7, 6) |
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#define HSPHY_CFG0_TRIMMASK (HSPHY_CFG0_HS_I_MASK \ |
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| HSPHY_CFG0_SEL_T_MASK \ |
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| HSPHY_CFG0_RTERM_MASK) |
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#define HSPHY_CFG1 0x4 |
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#define HSPHY_CFG1_DAT_EN BIT(29) |
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#define HSPHY_CFG1_ADR_EN BIT(28) |
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#define HSPHY_CFG1_ADR_MASK GENMASK(27, 16) |
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#define HSPHY_CFG1_DAT_MASK GENMASK(23, 16) |
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#define PHY_F(regno, msb, lsb) { (regno), (msb), (lsb) } |
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#define RX_CHK_SYNC PHY_F(0, 5, 5) /* RX sync mode */ |
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#define RX_SYNC_SEL PHY_F(1, 1, 0) /* RX sync length */ |
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#define LS_SLEW PHY_F(10, 6, 6) /* LS mode slew rate */ |
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#define FS_LS_DRV PHY_F(10, 5, 5) /* FS/LS slew rate */ |
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#define MAX_PHY_PARAMS 4 |
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struct uniphier_u3hsphy_param { |
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struct { |
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int reg_no; |
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int msb; |
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int lsb; |
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} field; |
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u8 value; |
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}; |
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struct uniphier_u3hsphy_trim_param { |
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unsigned int rterm; |
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unsigned int sel_t; |
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unsigned int hs_i; |
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}; |
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#define trim_param_is_valid(p) ((p)->rterm || (p)->sel_t || (p)->hs_i) |
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struct uniphier_u3hsphy_priv { |
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struct device *dev; |
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void __iomem *base; |
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struct clk *clk, *clk_parent, *clk_ext, *clk_parent_gio; |
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struct reset_control *rst, *rst_parent, *rst_parent_gio; |
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struct regulator *vbus; |
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const struct uniphier_u3hsphy_soc_data *data; |
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}; |
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struct uniphier_u3hsphy_soc_data { |
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bool is_legacy; |
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int nparams; |
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const struct uniphier_u3hsphy_param param[MAX_PHY_PARAMS]; |
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u32 config0; |
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u32 config1; |
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void (*trim_func)(struct uniphier_u3hsphy_priv *priv, u32 *pconfig, |
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struct uniphier_u3hsphy_trim_param *pt); |
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}; |
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static void uniphier_u3hsphy_trim_ld20(struct uniphier_u3hsphy_priv *priv, |
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u32 *pconfig, |
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struct uniphier_u3hsphy_trim_param *pt) |
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{ |
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*pconfig &= ~HSPHY_CFG0_RTERM_MASK; |
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*pconfig |= FIELD_PREP(HSPHY_CFG0_RTERM_MASK, pt->rterm); |
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*pconfig &= ~HSPHY_CFG0_SEL_T_MASK; |
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*pconfig |= FIELD_PREP(HSPHY_CFG0_SEL_T_MASK, pt->sel_t); |
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*pconfig &= ~HSPHY_CFG0_HS_I_MASK; |
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*pconfig |= FIELD_PREP(HSPHY_CFG0_HS_I_MASK, pt->hs_i); |
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} |
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static int uniphier_u3hsphy_get_nvparam(struct uniphier_u3hsphy_priv *priv, |
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const char *name, unsigned int *val) |
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{ |
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struct nvmem_cell *cell; |
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u8 *buf; |
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cell = devm_nvmem_cell_get(priv->dev, name); |
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if (IS_ERR(cell)) |
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return PTR_ERR(cell); |
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buf = nvmem_cell_read(cell, NULL); |
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if (IS_ERR(buf)) |
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return PTR_ERR(buf); |
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*val = *buf; |
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kfree(buf); |
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return 0; |
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} |
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static int uniphier_u3hsphy_get_nvparams(struct uniphier_u3hsphy_priv *priv, |
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struct uniphier_u3hsphy_trim_param *pt) |
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{ |
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int ret; |
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ret = uniphier_u3hsphy_get_nvparam(priv, "rterm", &pt->rterm); |
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if (ret) |
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return ret; |
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ret = uniphier_u3hsphy_get_nvparam(priv, "sel_t", &pt->sel_t); |
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if (ret) |
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return ret; |
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ret = uniphier_u3hsphy_get_nvparam(priv, "hs_i", &pt->hs_i); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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static int uniphier_u3hsphy_update_config(struct uniphier_u3hsphy_priv *priv, |
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u32 *pconfig) |
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{ |
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struct uniphier_u3hsphy_trim_param trim; |
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int ret, trimmed = 0; |
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if (priv->data->trim_func) { |
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ret = uniphier_u3hsphy_get_nvparams(priv, &trim); |
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if (ret == -EPROBE_DEFER) |
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return ret; |
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/* |
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* call trim_func only when trimming parameters that aren't |
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* all-zero can be acquired. All-zero parameters mean nothing |
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* has been written to nvmem. |
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*/ |
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if (!ret && trim_param_is_valid(&trim)) { |
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priv->data->trim_func(priv, pconfig, &trim); |
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trimmed = 1; |
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} else { |
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dev_dbg(priv->dev, "can't get parameter from nvmem\n"); |
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} |
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} |
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/* use default parameters without trimming values */ |
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if (!trimmed) { |
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*pconfig &= ~HSPHY_CFG0_HSDISC_MASK; |
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*pconfig |= FIELD_PREP(HSPHY_CFG0_HSDISC_MASK, 3); |
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} |
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return 0; |
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} |
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static void uniphier_u3hsphy_set_param(struct uniphier_u3hsphy_priv *priv, |
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const struct uniphier_u3hsphy_param *p) |
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{ |
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u32 val; |
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u32 field_mask = GENMASK(p->field.msb, p->field.lsb); |
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u8 data; |
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val = readl(priv->base + HSPHY_CFG1); |
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val &= ~HSPHY_CFG1_ADR_MASK; |
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val |= FIELD_PREP(HSPHY_CFG1_ADR_MASK, p->field.reg_no) |
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| HSPHY_CFG1_ADR_EN; |
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writel(val, priv->base + HSPHY_CFG1); |
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val = readl(priv->base + HSPHY_CFG1); |
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val &= ~HSPHY_CFG1_ADR_EN; |
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writel(val, priv->base + HSPHY_CFG1); |
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val = readl(priv->base + HSPHY_CFG1); |
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val &= ~FIELD_PREP(HSPHY_CFG1_DAT_MASK, field_mask); |
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data = field_mask & (p->value << p->field.lsb); |
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val |= FIELD_PREP(HSPHY_CFG1_DAT_MASK, data) | HSPHY_CFG1_DAT_EN; |
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writel(val, priv->base + HSPHY_CFG1); |
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val = readl(priv->base + HSPHY_CFG1); |
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val &= ~HSPHY_CFG1_DAT_EN; |
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writel(val, priv->base + HSPHY_CFG1); |
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} |
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static int uniphier_u3hsphy_power_on(struct phy *phy) |
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{ |
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struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy); |
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int ret; |
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ret = clk_prepare_enable(priv->clk_ext); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(priv->clk); |
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if (ret) |
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goto out_clk_ext_disable; |
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ret = reset_control_deassert(priv->rst); |
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if (ret) |
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goto out_clk_disable; |
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if (priv->vbus) { |
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ret = regulator_enable(priv->vbus); |
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if (ret) |
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goto out_rst_assert; |
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} |
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return 0; |
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out_rst_assert: |
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reset_control_assert(priv->rst); |
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out_clk_disable: |
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clk_disable_unprepare(priv->clk); |
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out_clk_ext_disable: |
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clk_disable_unprepare(priv->clk_ext); |
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return ret; |
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} |
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static int uniphier_u3hsphy_power_off(struct phy *phy) |
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{ |
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struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy); |
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if (priv->vbus) |
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regulator_disable(priv->vbus); |
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reset_control_assert(priv->rst); |
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clk_disable_unprepare(priv->clk); |
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clk_disable_unprepare(priv->clk_ext); |
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return 0; |
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} |
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static int uniphier_u3hsphy_init(struct phy *phy) |
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{ |
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struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy); |
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u32 config0, config1; |
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int i, ret; |
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ret = clk_prepare_enable(priv->clk_parent); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(priv->clk_parent_gio); |
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if (ret) |
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goto out_clk_disable; |
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ret = reset_control_deassert(priv->rst_parent); |
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if (ret) |
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goto out_clk_gio_disable; |
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ret = reset_control_deassert(priv->rst_parent_gio); |
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if (ret) |
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goto out_rst_assert; |
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if ((priv->data->is_legacy) |
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|| (!priv->data->config0 && !priv->data->config1)) |
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return 0; |
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config0 = priv->data->config0; |
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config1 = priv->data->config1; |
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ret = uniphier_u3hsphy_update_config(priv, &config0); |
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if (ret) |
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goto out_rst_assert; |
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writel(config0, priv->base + HSPHY_CFG0); |
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writel(config1, priv->base + HSPHY_CFG1); |
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for (i = 0; i < priv->data->nparams; i++) |
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uniphier_u3hsphy_set_param(priv, &priv->data->param[i]); |
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return 0; |
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out_rst_assert: |
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reset_control_assert(priv->rst_parent); |
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out_clk_gio_disable: |
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clk_disable_unprepare(priv->clk_parent_gio); |
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out_clk_disable: |
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clk_disable_unprepare(priv->clk_parent); |
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return ret; |
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} |
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static int uniphier_u3hsphy_exit(struct phy *phy) |
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{ |
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struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy); |
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reset_control_assert(priv->rst_parent_gio); |
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reset_control_assert(priv->rst_parent); |
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clk_disable_unprepare(priv->clk_parent_gio); |
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clk_disable_unprepare(priv->clk_parent); |
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return 0; |
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} |
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static const struct phy_ops uniphier_u3hsphy_ops = { |
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.init = uniphier_u3hsphy_init, |
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.exit = uniphier_u3hsphy_exit, |
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.power_on = uniphier_u3hsphy_power_on, |
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.power_off = uniphier_u3hsphy_power_off, |
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.owner = THIS_MODULE, |
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}; |
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static int uniphier_u3hsphy_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct uniphier_u3hsphy_priv *priv; |
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struct phy_provider *phy_provider; |
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struct phy *phy; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->dev = dev; |
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priv->data = of_device_get_match_data(dev); |
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if (WARN_ON(!priv->data || |
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priv->data->nparams > MAX_PHY_PARAMS)) |
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return -EINVAL; |
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priv->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(priv->base)) |
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return PTR_ERR(priv->base); |
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if (!priv->data->is_legacy) { |
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priv->clk = devm_clk_get(dev, "phy"); |
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if (IS_ERR(priv->clk)) |
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return PTR_ERR(priv->clk); |
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priv->clk_ext = devm_clk_get_optional(dev, "phy-ext"); |
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if (IS_ERR(priv->clk_ext)) |
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return PTR_ERR(priv->clk_ext); |
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priv->rst = devm_reset_control_get_shared(dev, "phy"); |
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if (IS_ERR(priv->rst)) |
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return PTR_ERR(priv->rst); |
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} else { |
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priv->clk_parent_gio = devm_clk_get(dev, "gio"); |
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if (IS_ERR(priv->clk_parent_gio)) |
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return PTR_ERR(priv->clk_parent_gio); |
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priv->rst_parent_gio = |
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devm_reset_control_get_shared(dev, "gio"); |
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if (IS_ERR(priv->rst_parent_gio)) |
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return PTR_ERR(priv->rst_parent_gio); |
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} |
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priv->clk_parent = devm_clk_get(dev, "link"); |
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if (IS_ERR(priv->clk_parent)) |
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return PTR_ERR(priv->clk_parent); |
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priv->rst_parent = devm_reset_control_get_shared(dev, "link"); |
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if (IS_ERR(priv->rst_parent)) |
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return PTR_ERR(priv->rst_parent); |
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priv->vbus = devm_regulator_get_optional(dev, "vbus"); |
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if (IS_ERR(priv->vbus)) { |
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if (PTR_ERR(priv->vbus) == -EPROBE_DEFER) |
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return PTR_ERR(priv->vbus); |
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priv->vbus = NULL; |
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} |
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phy = devm_phy_create(dev, dev->of_node, &uniphier_u3hsphy_ops); |
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if (IS_ERR(phy)) |
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return PTR_ERR(phy); |
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phy_set_drvdata(phy, priv); |
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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} |
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static const struct uniphier_u3hsphy_soc_data uniphier_pro5_data = { |
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.is_legacy = true, |
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.nparams = 0, |
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}; |
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static const struct uniphier_u3hsphy_soc_data uniphier_pxs2_data = { |
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.is_legacy = false, |
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.nparams = 2, |
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.param = { |
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{ RX_CHK_SYNC, 1 }, |
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{ RX_SYNC_SEL, 1 }, |
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}, |
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}; |
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static const struct uniphier_u3hsphy_soc_data uniphier_ld20_data = { |
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.is_legacy = false, |
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.nparams = 4, |
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.param = { |
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{ RX_CHK_SYNC, 1 }, |
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{ RX_SYNC_SEL, 1 }, |
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{ LS_SLEW, 1 }, |
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{ FS_LS_DRV, 1 }, |
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}, |
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.trim_func = uniphier_u3hsphy_trim_ld20, |
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.config0 = 0x92316680, |
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.config1 = 0x00000106, |
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}; |
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static const struct uniphier_u3hsphy_soc_data uniphier_pxs3_data = { |
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.is_legacy = false, |
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.nparams = 2, |
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.param = { |
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{ RX_CHK_SYNC, 1 }, |
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{ RX_SYNC_SEL, 1 }, |
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}, |
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.trim_func = uniphier_u3hsphy_trim_ld20, |
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.config0 = 0x92316680, |
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.config1 = 0x00000106, |
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}; |
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static const struct of_device_id uniphier_u3hsphy_match[] = { |
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{ |
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.compatible = "socionext,uniphier-pro5-usb3-hsphy", |
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.data = &uniphier_pro5_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pxs2-usb3-hsphy", |
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.data = &uniphier_pxs2_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-ld20-usb3-hsphy", |
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.data = &uniphier_ld20_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pxs3-usb3-hsphy", |
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.data = &uniphier_pxs3_data, |
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}, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, uniphier_u3hsphy_match); |
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static struct platform_driver uniphier_u3hsphy_driver = { |
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.probe = uniphier_u3hsphy_probe, |
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.driver = { |
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.name = "uniphier-usb3-hsphy", |
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.of_match_table = uniphier_u3hsphy_match, |
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}, |
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}; |
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module_platform_driver(uniphier_u3hsphy_driver); |
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MODULE_AUTHOR("Kunihiko Hayashi <[email protected]>"); |
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MODULE_DESCRIPTION("UniPhier HS-PHY driver for USB3 controller"); |
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MODULE_LICENSE("GPL v2");
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