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389 lines
11 KiB
389 lines
11 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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/* |
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* Rockchip MIPI Synopsys DPHY RX0 driver |
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* |
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* Copyright (C) 2019 Collabora, Ltd. |
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* |
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* Based on: |
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* |
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* drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c |
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* in https://chromium.googlesource.com/chromiumos/third_party/kernel, |
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* chromeos-4.4 branch. |
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* |
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* Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd. |
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* Jacob Chen <[email protected]> |
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* Shunqian Zheng <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/phy/phy.h> |
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#include <linux/phy/phy-mipi-dphy.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#define RK3399_GRF_SOC_CON9 0x6224 |
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#define RK3399_GRF_SOC_CON21 0x6254 |
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#define RK3399_GRF_SOC_CON22 0x6258 |
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#define RK3399_GRF_SOC_CON23 0x625c |
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#define RK3399_GRF_SOC_CON24 0x6260 |
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#define RK3399_GRF_SOC_CON25 0x6264 |
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#define RK3399_GRF_SOC_STATUS1 0xe2a4 |
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#define CLOCK_LANE_HS_RX_CONTROL 0x34 |
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#define LANE0_HS_RX_CONTROL 0x44 |
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#define LANE1_HS_RX_CONTROL 0x54 |
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#define LANE2_HS_RX_CONTROL 0x84 |
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#define LANE3_HS_RX_CONTROL 0x94 |
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#define LANES_THS_SETTLE_CONTROL 0x75 |
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#define THS_SETTLE_COUNTER_THRESHOLD 0x04 |
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struct hsfreq_range { |
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u16 range_h; |
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u8 cfg_bit; |
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}; |
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static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = { |
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{ 89, 0x00 }, { 99, 0x10 }, { 109, 0x20 }, { 129, 0x01 }, |
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{ 139, 0x11 }, { 149, 0x21 }, { 169, 0x02 }, { 179, 0x12 }, |
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{ 199, 0x22 }, { 219, 0x03 }, { 239, 0x13 }, { 249, 0x23 }, |
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{ 269, 0x04 }, { 299, 0x14 }, { 329, 0x05 }, { 359, 0x15 }, |
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{ 399, 0x25 }, { 449, 0x06 }, { 499, 0x16 }, { 549, 0x07 }, |
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{ 599, 0x17 }, { 649, 0x08 }, { 699, 0x18 }, { 749, 0x09 }, |
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{ 799, 0x19 }, { 849, 0x29 }, { 899, 0x39 }, { 949, 0x0a }, |
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{ 999, 0x1a }, { 1049, 0x2a }, { 1099, 0x3a }, { 1149, 0x0b }, |
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{ 1199, 0x1b }, { 1249, 0x2b }, { 1299, 0x3b }, { 1349, 0x0c }, |
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{ 1399, 0x1c }, { 1449, 0x2c }, { 1500, 0x3c } |
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}; |
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static const char * const rk3399_mipidphy_clks[] = { |
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"dphy-ref", |
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"dphy-cfg", |
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"grf", |
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}; |
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enum dphy_reg_id { |
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GRF_DPHY_RX0_TURNDISABLE = 0, |
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GRF_DPHY_RX0_FORCERXMODE, |
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GRF_DPHY_RX0_FORCETXSTOPMODE, |
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GRF_DPHY_RX0_ENABLE, |
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GRF_DPHY_RX0_TESTCLR, |
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GRF_DPHY_RX0_TESTCLK, |
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GRF_DPHY_RX0_TESTEN, |
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GRF_DPHY_RX0_TESTDIN, |
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GRF_DPHY_RX0_TURNREQUEST, |
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GRF_DPHY_RX0_TESTDOUT, |
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GRF_DPHY_TX0_TURNDISABLE, |
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GRF_DPHY_TX0_FORCERXMODE, |
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GRF_DPHY_TX0_FORCETXSTOPMODE, |
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GRF_DPHY_TX0_TURNREQUEST, |
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GRF_DPHY_TX1RX1_TURNDISABLE, |
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GRF_DPHY_TX1RX1_FORCERXMODE, |
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GRF_DPHY_TX1RX1_FORCETXSTOPMODE, |
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GRF_DPHY_TX1RX1_ENABLE, |
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GRF_DPHY_TX1RX1_MASTERSLAVEZ, |
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GRF_DPHY_TX1RX1_BASEDIR, |
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GRF_DPHY_TX1RX1_ENABLECLK, |
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GRF_DPHY_TX1RX1_TURNREQUEST, |
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GRF_DPHY_RX1_SRC_SEL, |
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/* rk3288 only */ |
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GRF_CON_DISABLE_ISP, |
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GRF_CON_ISP_DPHY_SEL, |
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GRF_DSI_CSI_TESTBUS_SEL, |
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GRF_DVP_V18SEL, |
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/* below is for rk3399 only */ |
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GRF_DPHY_RX0_CLK_INV_SEL, |
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GRF_DPHY_RX1_CLK_INV_SEL, |
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}; |
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struct dphy_reg { |
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u16 offset; |
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u8 mask; |
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u8 shift; |
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}; |
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#define PHY_REG(_offset, _width, _shift) \ |
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{ .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, } |
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static const struct dphy_reg rk3399_grf_dphy_regs[] = { |
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[GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0), |
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[GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10), |
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[GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11), |
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[GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0), |
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[GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4), |
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[GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8), |
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[GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12), |
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[GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0), |
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[GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4), |
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[GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 8), |
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[GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 12), |
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[GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 0), |
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[GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 4), |
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[GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 8), |
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[GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 12), |
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[GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON24, 4, 0), |
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[GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4), |
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[GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5), |
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[GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 6), |
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[GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 7), |
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[GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3399_GRF_SOC_CON25, 8, 0), |
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[GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 8), |
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[GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9), |
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[GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10), |
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[GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3399_GRF_SOC_STATUS1, 8, 0), |
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}; |
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struct rk_dphy_drv_data { |
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const char * const *clks; |
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unsigned int num_clks; |
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const struct hsfreq_range *hsfreq_ranges; |
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unsigned int num_hsfreq_ranges; |
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const struct dphy_reg *regs; |
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}; |
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struct rk_dphy { |
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struct device *dev; |
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struct regmap *grf; |
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struct clk_bulk_data *clks; |
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const struct rk_dphy_drv_data *drv_data; |
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struct phy_configure_opts_mipi_dphy config; |
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u8 hsfreq; |
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}; |
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static inline void rk_dphy_write_grf(struct rk_dphy *priv, |
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unsigned int index, u8 value) |
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{ |
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const struct dphy_reg *reg = &priv->drv_data->regs[index]; |
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/* Update high word */ |
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unsigned int val = (value << reg->shift) | |
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(reg->mask << (reg->shift + 16)); |
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if (WARN_ON(!reg->offset)) |
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return; |
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regmap_write(priv->grf, reg->offset, val); |
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} |
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static void rk_dphy_write(struct rk_dphy *priv, u8 test_code, u8 test_data) |
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{ |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTDIN, test_code); |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTEN, 1); |
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/* |
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* With the falling edge on TESTCLK, the TESTDIN[7:0] signal content |
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* is latched internally as the current test code. Test data is |
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* programmed internally by rising edge on TESTCLK. |
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* This code assumes that TESTCLK is already 1. |
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*/ |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLK, 0); |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTEN, 0); |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTDIN, test_data); |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLK, 1); |
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} |
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static void rk_dphy_enable(struct rk_dphy *priv) |
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{ |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_FORCERXMODE, 0); |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_FORCETXSTOPMODE, 0); |
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/* Disable lane turn around, which is ignored in receive mode */ |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_TURNREQUEST, 0); |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf); |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_ENABLE, |
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GENMASK(priv->config.lanes - 1, 0)); |
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/* dphy start */ |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLK, 1); |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLR, 1); |
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usleep_range(100, 150); |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLR, 0); |
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usleep_range(100, 150); |
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/* set clock lane */ |
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/* HS hsfreq_range & lane 0 settle bypass */ |
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rk_dphy_write(priv, CLOCK_LANE_HS_RX_CONTROL, 0); |
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/* HS RX Control of lane0 */ |
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rk_dphy_write(priv, LANE0_HS_RX_CONTROL, priv->hsfreq << 1); |
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/* HS RX Control of lane1 */ |
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rk_dphy_write(priv, LANE1_HS_RX_CONTROL, priv->hsfreq << 1); |
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/* HS RX Control of lane2 */ |
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rk_dphy_write(priv, LANE2_HS_RX_CONTROL, priv->hsfreq << 1); |
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/* HS RX Control of lane3 */ |
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rk_dphy_write(priv, LANE3_HS_RX_CONTROL, priv->hsfreq << 1); |
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/* HS RX Data Lanes Settle State Time Control */ |
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rk_dphy_write(priv, LANES_THS_SETTLE_CONTROL, |
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THS_SETTLE_COUNTER_THRESHOLD); |
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/* Normal operation */ |
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rk_dphy_write(priv, 0x0, 0); |
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} |
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static int rk_dphy_configure(struct phy *phy, union phy_configure_opts *opts) |
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{ |
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struct rk_dphy *priv = phy_get_drvdata(phy); |
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const struct rk_dphy_drv_data *drv_data = priv->drv_data; |
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struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy; |
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unsigned int hsfreq = 0; |
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unsigned int i; |
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u64 data_rate_mbps; |
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int ret; |
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/* pass with phy_mipi_dphy_get_default_config (with pixel rate?) */ |
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ret = phy_mipi_dphy_config_validate(config); |
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if (ret) |
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return ret; |
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data_rate_mbps = div_u64(config->hs_clk_rate, 1000 * 1000); |
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dev_dbg(priv->dev, "lanes %d - data_rate_mbps %llu\n", |
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config->lanes, data_rate_mbps); |
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for (i = 0; i < drv_data->num_hsfreq_ranges; i++) { |
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if (drv_data->hsfreq_ranges[i].range_h >= data_rate_mbps) { |
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hsfreq = drv_data->hsfreq_ranges[i].cfg_bit; |
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break; |
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} |
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} |
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if (!hsfreq) |
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return -EINVAL; |
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priv->hsfreq = hsfreq; |
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priv->config = *config; |
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return 0; |
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} |
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static int rk_dphy_power_on(struct phy *phy) |
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{ |
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struct rk_dphy *priv = phy_get_drvdata(phy); |
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int ret; |
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ret = clk_bulk_enable(priv->drv_data->num_clks, priv->clks); |
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if (ret) |
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return ret; |
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rk_dphy_enable(priv); |
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return 0; |
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} |
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static int rk_dphy_power_off(struct phy *phy) |
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{ |
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struct rk_dphy *priv = phy_get_drvdata(phy); |
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rk_dphy_write_grf(priv, GRF_DPHY_RX0_ENABLE, 0); |
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clk_bulk_disable(priv->drv_data->num_clks, priv->clks); |
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return 0; |
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} |
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static int rk_dphy_init(struct phy *phy) |
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{ |
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struct rk_dphy *priv = phy_get_drvdata(phy); |
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return clk_bulk_prepare(priv->drv_data->num_clks, priv->clks); |
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} |
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static int rk_dphy_exit(struct phy *phy) |
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{ |
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struct rk_dphy *priv = phy_get_drvdata(phy); |
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clk_bulk_unprepare(priv->drv_data->num_clks, priv->clks); |
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return 0; |
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} |
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static const struct phy_ops rk_dphy_ops = { |
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.power_on = rk_dphy_power_on, |
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.power_off = rk_dphy_power_off, |
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.init = rk_dphy_init, |
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.exit = rk_dphy_exit, |
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.configure = rk_dphy_configure, |
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.owner = THIS_MODULE, |
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}; |
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static const struct rk_dphy_drv_data rk3399_mipidphy_drv_data = { |
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.clks = rk3399_mipidphy_clks, |
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.num_clks = ARRAY_SIZE(rk3399_mipidphy_clks), |
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.hsfreq_ranges = rk3399_mipidphy_hsfreq_ranges, |
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.num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges), |
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.regs = rk3399_grf_dphy_regs, |
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}; |
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static const struct of_device_id rk_dphy_dt_ids[] = { |
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{ |
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.compatible = "rockchip,rk3399-mipi-dphy-rx0", |
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.data = &rk3399_mipidphy_drv_data, |
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}, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, rk_dphy_dt_ids); |
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static int rk_dphy_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *np = dev->of_node; |
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const struct rk_dphy_drv_data *drv_data; |
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struct phy_provider *phy_provider; |
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const struct of_device_id *of_id; |
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struct rk_dphy *priv; |
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struct phy *phy; |
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unsigned int i; |
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int ret; |
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if (!dev->parent || !dev->parent->of_node) |
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return -ENODEV; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->dev = dev; |
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priv->grf = syscon_node_to_regmap(dev->parent->of_node); |
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if (IS_ERR(priv->grf)) { |
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dev_err(dev, "Can't find GRF syscon\n"); |
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return -ENODEV; |
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} |
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of_id = of_match_device(rk_dphy_dt_ids, dev); |
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if (!of_id) |
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return -EINVAL; |
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drv_data = of_id->data; |
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priv->drv_data = drv_data; |
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priv->clks = devm_kcalloc(&pdev->dev, drv_data->num_clks, |
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sizeof(*priv->clks), GFP_KERNEL); |
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if (!priv->clks) |
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return -ENOMEM; |
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for (i = 0; i < drv_data->num_clks; i++) |
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priv->clks[i].id = drv_data->clks[i]; |
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ret = devm_clk_bulk_get(&pdev->dev, drv_data->num_clks, priv->clks); |
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if (ret) |
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return ret; |
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phy = devm_phy_create(dev, np, &rk_dphy_ops); |
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if (IS_ERR(phy)) { |
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dev_err(dev, "failed to create phy\n"); |
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return PTR_ERR(phy); |
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} |
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phy_set_drvdata(phy, priv); |
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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} |
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static struct platform_driver rk_dphy_driver = { |
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.probe = rk_dphy_probe, |
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.driver = { |
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.name = "rockchip-mipi-dphy-rx0", |
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.of_match_table = rk_dphy_dt_ids, |
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}, |
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}; |
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module_platform_driver(rk_dphy_driver); |
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MODULE_AUTHOR("Ezequiel Garcia <[email protected]>"); |
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MODULE_DESCRIPTION("Rockchip MIPI Synopsys DPHY RX0 driver"); |
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MODULE_LICENSE("Dual MIT/GPL");
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