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661 lines
15 KiB
661 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Phy provider for USB 3.1 controller on HiSilicon Kirin970 platform |
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* |
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* Copyright (C) 2017-2020 Hilisicon Electronics Co., Ltd. |
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* http://www.huawei.com |
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* |
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* Authors: Yu Chen <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <linux/kernel.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#define SCTRL_SCDEEPSLEEPED (0x0) |
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#define USB_CLK_SELECTED BIT(20) |
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#define PERI_CRG_PEREN0 (0x00) |
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#define PERI_CRG_PERDIS0 (0x04) |
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#define PERI_CRG_PEREN4 (0x40) |
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#define PERI_CRG_PERDIS4 (0x44) |
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#define PERI_CRG_PERRSTEN4 (0x90) |
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#define PERI_CRG_PERRSTDIS4 (0x94) |
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#define PERI_CRG_ISODIS (0x148) |
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#define PERI_CRG_PEREN6 (0x410) |
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#define PERI_CRG_PERDIS6 (0x414) |
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#define USB_REFCLK_ISO_EN BIT(25) |
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#define GT_CLK_USB2PHY_REF BIT(19) |
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#define PCTRL_PERI_CTRL3 (0x10) |
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#define PCTRL_PERI_CTRL3_MSK_START (16) |
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#define USB_TCXO_EN BIT(1) |
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#define PCTRL_PERI_CTRL24 (0x64) |
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#define SC_CLK_USB3PHY_3MUX1_SEL BIT(25) |
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#define USB3OTG_CTRL0 (0x00) |
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#define USB3OTG_CTRL3 (0x0c) |
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#define USB3OTG_CTRL4 (0x10) |
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#define USB3OTG_CTRL5 (0x14) |
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#define USB3OTG_CTRL7 (0x1c) |
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#define USB_MISC_CFG50 (0x50) |
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#define USB_MISC_CFG54 (0x54) |
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#define USB_MISC_CFG58 (0x58) |
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#define USB_MISC_CFG5C (0x5c) |
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#define USB_MISC_CFGA0 (0xa0) |
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#define TCA_CLK_RST (0x200) |
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#define TCA_INTR_EN (0x204) |
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#define TCA_INTR_STS (0x208) |
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#define TCA_GCFG (0x210) |
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#define TCA_TCPC (0x214) |
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#define TCA_SYSMODE_CFG (0x218) |
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#define TCA_VBUS_CTRL (0x240) |
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#define CTRL0_USB3_VBUSVLD BIT(7) |
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#define CTRL0_USB3_VBUSVLD_SEL BIT(6) |
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#define CTRL3_USB2_VBUSVLDEXT0 BIT(6) |
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#define CTRL3_USB2_VBUSVLDEXTSEL0 BIT(5) |
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#define CTRL5_USB2_SIDDQ BIT(0) |
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#define CTRL7_USB2_REFCLKSEL_MASK GENMASK(4, 3) |
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#define CTRL7_USB2_REFCLKSEL_ABB (BIT(4) | BIT(3)) |
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#define CTRL7_USB2_REFCLKSEL_PAD BIT(4) |
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#define CFG50_USB3_PHY_TEST_POWERDOWN BIT(23) |
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#define CFG54_USB31PHY_CR_ADDR_MASK GENMASK(31, 16) |
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#define CFG54_USB3PHY_REF_USE_PAD BIT(12) |
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#define CFG54_PHY0_PMA_PWR_STABLE BIT(11) |
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#define CFG54_PHY0_PCS_PWR_STABLE BIT(9) |
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#define CFG54_USB31PHY_CR_ACK BIT(7) |
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#define CFG54_USB31PHY_CR_WR_EN BIT(5) |
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#define CFG54_USB31PHY_CR_SEL BIT(4) |
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#define CFG54_USB31PHY_CR_RD_EN BIT(3) |
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#define CFG54_USB31PHY_CR_CLK BIT(2) |
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#define CFG54_USB3_PHY0_ANA_PWR_EN BIT(1) |
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#define CFG58_USB31PHY_CR_DATA_MASK GENMASK(31, 16) |
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#define CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN BIT(1) |
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#define CFGA0_VAUX_RESET BIT(9) |
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#define CFGA0_USB31C_RESET BIT(8) |
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#define CFGA0_USB2PHY_REFCLK_SELECT BIT(4) |
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#define CFGA0_USB3PHY_RESET BIT(1) |
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#define CFGA0_USB2PHY_POR BIT(0) |
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#define INTR_EN_XA_TIMEOUT_EVT_EN BIT(1) |
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#define INTR_EN_XA_ACK_EVT_EN BIT(0) |
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#define CLK_RST_TCA_REF_CLK_EN BIT(1) |
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#define CLK_RST_SUSPEND_CLK_EN BIT(0) |
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#define GCFG_ROLE_HSTDEV BIT(4) |
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#define GCFG_OP_MODE GENMASK(1, 0) |
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#define GCFG_OP_MODE_CTRL_SYNC_MODE BIT(0) |
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#define TCPC_VALID BIT(4) |
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#define TCPC_LOW_POWER_EN BIT(3) |
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#define TCPC_MUX_CONTROL_MASK GENMASK(1, 0) |
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#define TCPC_MUX_CONTROL_USB31 BIT(0) |
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#define SYSMODE_CFG_TYPEC_DISABLE BIT(3) |
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#define VBUS_CTRL_POWERPRESENT_OVERRD GENMASK(3, 2) |
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#define VBUS_CTRL_VBUSVALID_OVERRD GENMASK(1, 0) |
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#define KIRIN970_USB_DEFAULT_PHY_PARAM (0xfdfee4) |
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#define KIRIN970_USB_DEFAULT_PHY_VBOOST (0x5) |
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#define TX_VBOOST_LVL_REG (0xf) |
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#define TX_VBOOST_LVL_START (6) |
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#define TX_VBOOST_LVL_ENABLE BIT(9) |
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struct hi3670_priv { |
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struct device *dev; |
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struct regmap *peri_crg; |
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struct regmap *pctrl; |
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struct regmap *sctrl; |
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struct regmap *usb31misc; |
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u32 eye_diagram_param; |
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u32 tx_vboost_lvl; |
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u32 peri_crg_offset; |
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u32 pctrl_offset; |
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u32 usb31misc_offset; |
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}; |
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static int hi3670_phy_cr_clk(struct regmap *usb31misc) |
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{ |
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int ret; |
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/* Clock up */ |
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ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, |
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CFG54_USB31PHY_CR_CLK, CFG54_USB31PHY_CR_CLK); |
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if (ret) |
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return ret; |
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/* Clock down */ |
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return regmap_update_bits(usb31misc, USB_MISC_CFG54, |
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CFG54_USB31PHY_CR_CLK, 0); |
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} |
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static int hi3670_phy_cr_set_sel(struct regmap *usb31misc) |
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{ |
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return regmap_update_bits(usb31misc, USB_MISC_CFG54, |
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CFG54_USB31PHY_CR_SEL, CFG54_USB31PHY_CR_SEL); |
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} |
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static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction) |
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{ |
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int ret, reg; |
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if (direction) |
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reg = CFG54_USB31PHY_CR_WR_EN; |
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else |
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reg = CFG54_USB31PHY_CR_RD_EN; |
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ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, reg, reg); |
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if (ret) |
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return ret; |
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ret = hi3670_phy_cr_clk(usb31misc); |
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if (ret) |
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return ret; |
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return regmap_update_bits(usb31misc, USB_MISC_CFG54, |
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CFG54_USB31PHY_CR_RD_EN | CFG54_USB31PHY_CR_WR_EN, 0); |
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} |
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static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc) |
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{ |
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u32 reg; |
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int retry = 10; |
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int ret; |
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while (retry-- > 0) { |
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ret = regmap_read(usb31misc, USB_MISC_CFG54, ®); |
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if (ret) |
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return ret; |
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if ((reg & CFG54_USB31PHY_CR_ACK) == CFG54_USB31PHY_CR_ACK) |
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return 0; |
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ret = hi3670_phy_cr_clk(usb31misc); |
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if (ret) |
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return ret; |
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usleep_range(10, 20); |
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} |
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return -ETIMEDOUT; |
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} |
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static int hi3670_phy_cr_set_addr(struct regmap *usb31misc, u32 addr) |
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{ |
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u32 reg; |
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int ret; |
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ret = regmap_read(usb31misc, USB_MISC_CFG54, ®); |
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if (ret) |
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return ret; |
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reg = FIELD_PREP(CFG54_USB31PHY_CR_ADDR_MASK, addr); |
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return regmap_update_bits(usb31misc, USB_MISC_CFG54, |
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CFG54_USB31PHY_CR_ADDR_MASK, reg); |
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} |
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static int hi3670_phy_cr_read(struct regmap *usb31misc, u32 addr, u32 *val) |
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{ |
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int reg, i, ret; |
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for (i = 0; i < 100; i++) { |
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ret = hi3670_phy_cr_clk(usb31misc); |
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if (ret) |
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return ret; |
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} |
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ret = hi3670_phy_cr_set_sel(usb31misc); |
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if (ret) |
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return ret; |
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ret = hi3670_phy_cr_set_addr(usb31misc, addr); |
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if (ret) |
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return ret; |
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ret = hi3670_phy_cr_start(usb31misc, 0); |
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if (ret) |
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return ret; |
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ret = hi3670_phy_cr_wait_ack(usb31misc); |
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if (ret) |
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return ret; |
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ret = regmap_read(usb31misc, USB_MISC_CFG58, ®); |
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if (ret) |
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return ret; |
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*val = FIELD_GET(CFG58_USB31PHY_CR_DATA_MASK, reg); |
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return 0; |
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} |
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static int hi3670_phy_cr_write(struct regmap *usb31misc, u32 addr, u32 val) |
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{ |
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int i; |
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int ret; |
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for (i = 0; i < 100; i++) { |
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ret = hi3670_phy_cr_clk(usb31misc); |
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if (ret) |
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return ret; |
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} |
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ret = hi3670_phy_cr_set_sel(usb31misc); |
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if (ret) |
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return ret; |
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ret = hi3670_phy_cr_set_addr(usb31misc, addr); |
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if (ret) |
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return ret; |
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ret = regmap_write(usb31misc, USB_MISC_CFG58, |
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FIELD_PREP(CFG58_USB31PHY_CR_DATA_MASK, val)); |
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if (ret) |
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return ret; |
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ret = hi3670_phy_cr_start(usb31misc, 1); |
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if (ret) |
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return ret; |
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return hi3670_phy_cr_wait_ack(usb31misc); |
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} |
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static int hi3670_phy_set_params(struct hi3670_priv *priv) |
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{ |
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u32 reg; |
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int ret; |
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int retry = 3; |
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ret = regmap_write(priv->usb31misc, USB3OTG_CTRL4, |
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priv->eye_diagram_param); |
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if (ret) { |
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dev_err(priv->dev, "set USB3OTG_CTRL4 failed\n"); |
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return ret; |
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} |
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while (retry-- > 0) { |
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ret = hi3670_phy_cr_read(priv->usb31misc, |
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TX_VBOOST_LVL_REG, ®); |
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if (!ret) |
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break; |
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if (ret != -ETIMEDOUT) { |
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dev_err(priv->dev, "read TX_VBOOST_LVL_REG failed\n"); |
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return ret; |
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} |
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} |
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if (ret) |
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return ret; |
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reg |= (TX_VBOOST_LVL_ENABLE | (priv->tx_vboost_lvl << TX_VBOOST_LVL_START)); |
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ret = hi3670_phy_cr_write(priv->usb31misc, TX_VBOOST_LVL_REG, reg); |
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if (ret) |
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dev_err(priv->dev, "write TX_VBOOST_LVL_REG failed\n"); |
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return ret; |
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} |
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static bool hi3670_is_abbclk_selected(struct hi3670_priv *priv) |
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{ |
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u32 reg; |
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if (!priv->sctrl) { |
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dev_err(priv->dev, "priv->sctrl is null!\n"); |
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return false; |
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} |
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if (regmap_read(priv->sctrl, SCTRL_SCDEEPSLEEPED, ®)) { |
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dev_err(priv->dev, "SCTRL_SCDEEPSLEEPED read failed!\n"); |
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return false; |
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} |
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if ((reg & USB_CLK_SELECTED) == 0) |
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return false; |
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return true; |
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} |
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static int hi3670_config_phy_clock(struct hi3670_priv *priv) |
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{ |
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u32 val, mask; |
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int ret; |
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if (!hi3670_is_abbclk_selected(priv)) { |
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/* usb refclk iso disable */ |
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ret = regmap_write(priv->peri_crg, PERI_CRG_ISODIS, |
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USB_REFCLK_ISO_EN); |
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if (ret) |
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goto out; |
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/* enable usb_tcxo_en */ |
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ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, |
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USB_TCXO_EN | |
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(USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START)); |
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/* select usbphy clk from abb */ |
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mask = SC_CLK_USB3PHY_3MUX1_SEL; |
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ret = regmap_update_bits(priv->pctrl, |
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PCTRL_PERI_CTRL24, mask, 0); |
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if (ret) |
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goto out; |
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ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, |
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CFGA0_USB2PHY_REFCLK_SELECT, 0); |
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if (ret) |
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goto out; |
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ret = regmap_read(priv->usb31misc, USB3OTG_CTRL7, &val); |
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if (ret) |
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goto out; |
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val &= ~CTRL7_USB2_REFCLKSEL_MASK; |
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val |= CTRL7_USB2_REFCLKSEL_ABB; |
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ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val); |
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if (ret) |
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goto out; |
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return 0; |
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} |
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ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54, |
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CFG54_USB3PHY_REF_USE_PAD, |
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CFG54_USB3PHY_REF_USE_PAD); |
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if (ret) |
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goto out; |
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ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, |
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CFGA0_USB2PHY_REFCLK_SELECT, |
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CFGA0_USB2PHY_REFCLK_SELECT); |
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if (ret) |
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goto out; |
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ret = regmap_read(priv->usb31misc, USB3OTG_CTRL7, &val); |
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if (ret) |
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goto out; |
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val &= ~CTRL7_USB2_REFCLKSEL_MASK; |
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val |= CTRL7_USB2_REFCLKSEL_PAD; |
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ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val); |
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if (ret) |
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goto out; |
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ret = regmap_write(priv->peri_crg, |
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PERI_CRG_PEREN6, GT_CLK_USB2PHY_REF); |
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if (ret) |
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goto out; |
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return 0; |
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out: |
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dev_err(priv->dev, "failed to config phy clock ret: %d\n", ret); |
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return ret; |
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} |
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static int hi3670_config_tca(struct hi3670_priv *priv) |
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{ |
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u32 val, mask; |
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int ret; |
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ret = regmap_write(priv->usb31misc, TCA_INTR_STS, 0xffff); |
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if (ret) |
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goto out; |
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ret = regmap_write(priv->usb31misc, TCA_INTR_EN, |
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INTR_EN_XA_TIMEOUT_EVT_EN | INTR_EN_XA_ACK_EVT_EN); |
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if (ret) |
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goto out; |
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mask = CLK_RST_TCA_REF_CLK_EN | CLK_RST_SUSPEND_CLK_EN; |
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ret = regmap_update_bits(priv->usb31misc, TCA_CLK_RST, mask, 0); |
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if (ret) |
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goto out; |
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ret = regmap_update_bits(priv->usb31misc, TCA_GCFG, |
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GCFG_ROLE_HSTDEV | GCFG_OP_MODE, |
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GCFG_ROLE_HSTDEV | GCFG_OP_MODE_CTRL_SYNC_MODE); |
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if (ret) |
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goto out; |
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ret = regmap_update_bits(priv->usb31misc, TCA_SYSMODE_CFG, |
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SYSMODE_CFG_TYPEC_DISABLE, 0); |
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if (ret) |
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goto out; |
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ret = regmap_read(priv->usb31misc, TCA_TCPC, &val); |
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if (ret) |
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goto out; |
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val &= ~(TCPC_VALID | TCPC_LOW_POWER_EN | TCPC_MUX_CONTROL_MASK); |
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val |= (TCPC_VALID | TCPC_MUX_CONTROL_USB31); |
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ret = regmap_write(priv->usb31misc, TCA_TCPC, val); |
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if (ret) |
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goto out; |
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ret = regmap_write(priv->usb31misc, TCA_VBUS_CTRL, |
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VBUS_CTRL_POWERPRESENT_OVERRD | VBUS_CTRL_VBUSVALID_OVERRD); |
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if (ret) |
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goto out; |
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return 0; |
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out: |
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dev_err(priv->dev, "failed to config phy clock ret: %d\n", ret); |
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return ret; |
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} |
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static int hi3670_phy_init(struct phy *phy) |
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{ |
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struct hi3670_priv *priv = phy_get_drvdata(phy); |
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u32 val; |
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int ret; |
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/* assert controller */ |
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val = CFGA0_VAUX_RESET | CFGA0_USB31C_RESET | |
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CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; |
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ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, 0); |
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if (ret) |
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goto out; |
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ret = hi3670_config_phy_clock(priv); |
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if (ret) |
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goto out; |
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/* Exit from IDDQ mode */ |
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ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL5, |
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CTRL5_USB2_SIDDQ, 0); |
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if (ret) |
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goto out; |
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/* Release USB31 PHY out of TestPowerDown mode */ |
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ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG50, |
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CFG50_USB3_PHY_TEST_POWERDOWN, 0); |
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if (ret) |
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goto out; |
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/* Deassert phy */ |
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val = CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; |
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ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, val); |
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if (ret) |
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goto out; |
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usleep_range(100, 120); |
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/* Tell the PHY power is stable */ |
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val = CFG54_USB3_PHY0_ANA_PWR_EN | CFG54_PHY0_PCS_PWR_STABLE | |
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CFG54_PHY0_PMA_PWR_STABLE; |
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ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54, |
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val, val); |
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if (ret) |
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goto out; |
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ret = hi3670_config_tca(priv); |
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if (ret) |
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goto out; |
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/* Enable SSC */ |
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ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG5C, |
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CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN, |
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CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN); |
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if (ret) |
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goto out; |
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/* Deassert controller */ |
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val = CFGA0_VAUX_RESET | CFGA0_USB31C_RESET; |
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ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, val); |
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if (ret) |
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goto out; |
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usleep_range(100, 120); |
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/* Set fake vbus valid signal */ |
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val = CTRL0_USB3_VBUSVLD | CTRL0_USB3_VBUSVLD_SEL; |
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ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL0, val, val); |
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if (ret) |
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goto out; |
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val = CTRL3_USB2_VBUSVLDEXT0 | CTRL3_USB2_VBUSVLDEXTSEL0; |
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ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL3, val, val); |
|
if (ret) |
|
goto out; |
|
|
|
usleep_range(100, 120); |
|
|
|
ret = hi3670_phy_set_params(priv); |
|
if (ret) |
|
goto out; |
|
|
|
return 0; |
|
out: |
|
dev_err(priv->dev, "failed to init phy ret: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
static int hi3670_phy_exit(struct phy *phy) |
|
{ |
|
struct hi3670_priv *priv = phy_get_drvdata(phy); |
|
u32 mask; |
|
int ret; |
|
|
|
/* Assert phy */ |
|
mask = CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; |
|
ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, mask, 0); |
|
if (ret) |
|
goto out; |
|
|
|
if (!hi3670_is_abbclk_selected(priv)) { |
|
/* disable usb_tcxo_en */ |
|
ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, |
|
USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START); |
|
} else { |
|
ret = regmap_write(priv->peri_crg, PERI_CRG_PERDIS6, |
|
GT_CLK_USB2PHY_REF); |
|
if (ret) |
|
goto out; |
|
} |
|
|
|
return 0; |
|
out: |
|
dev_err(priv->dev, "failed to exit phy ret: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
static const struct phy_ops hi3670_phy_ops = { |
|
.init = hi3670_phy_init, |
|
.exit = hi3670_phy_exit, |
|
.owner = THIS_MODULE, |
|
}; |
|
|
|
static int hi3670_phy_probe(struct platform_device *pdev) |
|
{ |
|
struct phy_provider *phy_provider; |
|
struct device *dev = &pdev->dev; |
|
struct phy *phy; |
|
struct hi3670_priv *priv; |
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
|
if (!priv) |
|
return -ENOMEM; |
|
|
|
priv->dev = dev; |
|
priv->peri_crg = syscon_regmap_lookup_by_phandle(dev->of_node, |
|
"hisilicon,pericrg-syscon"); |
|
if (IS_ERR(priv->peri_crg)) { |
|
dev_err(dev, "no hisilicon,pericrg-syscon\n"); |
|
return PTR_ERR(priv->peri_crg); |
|
} |
|
|
|
priv->pctrl = syscon_regmap_lookup_by_phandle(dev->of_node, |
|
"hisilicon,pctrl-syscon"); |
|
if (IS_ERR(priv->pctrl)) { |
|
dev_err(dev, "no hisilicon,pctrl-syscon\n"); |
|
return PTR_ERR(priv->pctrl); |
|
} |
|
|
|
priv->sctrl = syscon_regmap_lookup_by_phandle(dev->of_node, |
|
"hisilicon,sctrl-syscon"); |
|
if (IS_ERR(priv->sctrl)) { |
|
dev_err(dev, "no hisilicon,sctrl-syscon\n"); |
|
return PTR_ERR(priv->sctrl); |
|
} |
|
|
|
/* node of hi3670 phy is a sub-node of usb3_otg_bc */ |
|
priv->usb31misc = syscon_node_to_regmap(dev->parent->of_node); |
|
if (IS_ERR(priv->usb31misc)) { |
|
dev_err(dev, "no hisilicon,usb3-otg-bc-syscon\n"); |
|
return PTR_ERR(priv->usb31misc); |
|
} |
|
|
|
if (of_property_read_u32(dev->of_node, "hisilicon,eye-diagram-param", |
|
&priv->eye_diagram_param)) |
|
priv->eye_diagram_param = KIRIN970_USB_DEFAULT_PHY_PARAM; |
|
|
|
if (of_property_read_u32(dev->of_node, "hisilicon,tx-vboost-lvl", |
|
&priv->tx_vboost_lvl)) |
|
priv->tx_vboost_lvl = KIRIN970_USB_DEFAULT_PHY_VBOOST; |
|
|
|
phy = devm_phy_create(dev, NULL, &hi3670_phy_ops); |
|
if (IS_ERR(phy)) |
|
return PTR_ERR(phy); |
|
|
|
phy_set_drvdata(phy, priv); |
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
|
return PTR_ERR_OR_ZERO(phy_provider); |
|
} |
|
|
|
static const struct of_device_id hi3670_phy_of_match[] = { |
|
{ .compatible = "hisilicon,hi3670-usb-phy" }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, hi3670_phy_of_match); |
|
|
|
static struct platform_driver hi3670_phy_driver = { |
|
.probe = hi3670_phy_probe, |
|
.driver = { |
|
.name = "hi3670-usb-phy", |
|
.of_match_table = hi3670_phy_of_match, |
|
} |
|
}; |
|
module_platform_driver(hi3670_phy_driver); |
|
|
|
MODULE_AUTHOR("Yu Chen <[email protected]>"); |
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_DESCRIPTION("Hilisicon Kirin970 USB31 PHY Driver");
|
|
|