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875 lines
22 KiB
875 lines
22 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* ARM DynamIQ Shared Unit (DSU) PMU driver |
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* |
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* Copyright (C) ARM Limited, 2017. |
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* |
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* Based on ARM CCI-PMU, ARMv8 PMU-v3 drivers. |
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*/ |
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#define PMUNAME "arm_dsu" |
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#define DRVNAME PMUNAME "_pmu" |
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#define pr_fmt(fmt) DRVNAME ": " fmt |
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#include <linux/acpi.h> |
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#include <linux/bitmap.h> |
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#include <linux/bitops.h> |
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#include <linux/bug.h> |
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#include <linux/cpumask.h> |
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#include <linux/device.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/perf_event.h> |
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#include <linux/platform_device.h> |
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#include <linux/spinlock.h> |
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#include <linux/smp.h> |
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#include <linux/sysfs.h> |
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#include <linux/types.h> |
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#include <asm/arm_dsu_pmu.h> |
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#include <asm/local64.h> |
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/* PMU event codes */ |
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#define DSU_PMU_EVT_CYCLES 0x11 |
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#define DSU_PMU_EVT_CHAIN 0x1e |
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#define DSU_PMU_MAX_COMMON_EVENTS 0x40 |
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#define DSU_PMU_MAX_HW_CNTRS 32 |
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#define DSU_PMU_HW_COUNTER_MASK (DSU_PMU_MAX_HW_CNTRS - 1) |
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#define CLUSTERPMCR_E BIT(0) |
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#define CLUSTERPMCR_P BIT(1) |
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#define CLUSTERPMCR_C BIT(2) |
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#define CLUSTERPMCR_N_SHIFT 11 |
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#define CLUSTERPMCR_N_MASK 0x1f |
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#define CLUSTERPMCR_IDCODE_SHIFT 16 |
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#define CLUSTERPMCR_IDCODE_MASK 0xff |
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#define CLUSTERPMCR_IMP_SHIFT 24 |
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#define CLUSTERPMCR_IMP_MASK 0xff |
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#define CLUSTERPMCR_RES_MASK 0x7e8 |
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#define CLUSTERPMCR_RES_VAL 0x40 |
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#define DSU_ACTIVE_CPU_MASK 0x0 |
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#define DSU_ASSOCIATED_CPU_MASK 0x1 |
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/* |
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* We use the index of the counters as they appear in the counter |
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* bit maps in the PMU registers (e.g CLUSTERPMSELR). |
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* i.e, |
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* counter 0 - Bit 0 |
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* counter 1 - Bit 1 |
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* ... |
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* Cycle counter - Bit 31 |
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*/ |
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#define DSU_PMU_IDX_CYCLE_COUNTER 31 |
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/* All event counters are 32bit, with a 64bit Cycle counter */ |
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#define DSU_PMU_COUNTER_WIDTH(idx) \ |
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(((idx) == DSU_PMU_IDX_CYCLE_COUNTER) ? 64 : 32) |
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#define DSU_PMU_COUNTER_MASK(idx) \ |
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GENMASK_ULL((DSU_PMU_COUNTER_WIDTH((idx)) - 1), 0) |
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#define DSU_EXT_ATTR(_name, _func, _config) \ |
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(&((struct dev_ext_attribute[]) { \ |
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{ \ |
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.attr = __ATTR(_name, 0444, _func, NULL), \ |
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.var = (void *)_config \ |
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} \ |
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})[0].attr.attr) |
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#define DSU_EVENT_ATTR(_name, _config) \ |
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DSU_EXT_ATTR(_name, dsu_pmu_sysfs_event_show, (unsigned long)_config) |
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#define DSU_FORMAT_ATTR(_name, _config) \ |
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DSU_EXT_ATTR(_name, dsu_pmu_sysfs_format_show, (char *)_config) |
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#define DSU_CPUMASK_ATTR(_name, _config) \ |
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DSU_EXT_ATTR(_name, dsu_pmu_cpumask_show, (unsigned long)_config) |
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struct dsu_hw_events { |
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DECLARE_BITMAP(used_mask, DSU_PMU_MAX_HW_CNTRS); |
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struct perf_event *events[DSU_PMU_MAX_HW_CNTRS]; |
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}; |
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/* |
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* struct dsu_pmu - DSU PMU descriptor |
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* |
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* @pmu_lock : Protects accesses to DSU PMU register from normal vs |
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* interrupt handler contexts. |
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* @hw_events : Holds the event counter state. |
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* @associated_cpus : CPUs attached to the DSU. |
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* @active_cpu : CPU to which the PMU is bound for accesses. |
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* @cpuhp_node : Node for CPU hotplug notifier link. |
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* @num_counters : Number of event counters implemented by the PMU, |
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* excluding the cycle counter. |
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* @irq : Interrupt line for counter overflow. |
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* @cpmceid_bitmap : Bitmap for the availability of architected common |
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* events (event_code < 0x40). |
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*/ |
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struct dsu_pmu { |
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struct pmu pmu; |
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struct device *dev; |
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raw_spinlock_t pmu_lock; |
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struct dsu_hw_events hw_events; |
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cpumask_t associated_cpus; |
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cpumask_t active_cpu; |
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struct hlist_node cpuhp_node; |
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s8 num_counters; |
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int irq; |
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DECLARE_BITMAP(cpmceid_bitmap, DSU_PMU_MAX_COMMON_EVENTS); |
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}; |
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static unsigned long dsu_pmu_cpuhp_state; |
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static inline struct dsu_pmu *to_dsu_pmu(struct pmu *pmu) |
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{ |
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return container_of(pmu, struct dsu_pmu, pmu); |
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} |
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static ssize_t dsu_pmu_sysfs_event_show(struct device *dev, |
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struct device_attribute *attr, |
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char *buf) |
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{ |
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struct dev_ext_attribute *eattr = container_of(attr, |
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struct dev_ext_attribute, attr); |
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return sysfs_emit(buf, "event=0x%lx\n", (unsigned long)eattr->var); |
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} |
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static ssize_t dsu_pmu_sysfs_format_show(struct device *dev, |
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struct device_attribute *attr, |
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char *buf) |
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{ |
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struct dev_ext_attribute *eattr = container_of(attr, |
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struct dev_ext_attribute, attr); |
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return sysfs_emit(buf, "%s\n", (char *)eattr->var); |
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} |
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static ssize_t dsu_pmu_cpumask_show(struct device *dev, |
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struct device_attribute *attr, |
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char *buf) |
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{ |
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struct pmu *pmu = dev_get_drvdata(dev); |
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struct dsu_pmu *dsu_pmu = to_dsu_pmu(pmu); |
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struct dev_ext_attribute *eattr = container_of(attr, |
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struct dev_ext_attribute, attr); |
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unsigned long mask_id = (unsigned long)eattr->var; |
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const cpumask_t *cpumask; |
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switch (mask_id) { |
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case DSU_ACTIVE_CPU_MASK: |
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cpumask = &dsu_pmu->active_cpu; |
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break; |
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case DSU_ASSOCIATED_CPU_MASK: |
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cpumask = &dsu_pmu->associated_cpus; |
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break; |
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default: |
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return 0; |
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} |
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return cpumap_print_to_pagebuf(true, buf, cpumask); |
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} |
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static struct attribute *dsu_pmu_format_attrs[] = { |
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DSU_FORMAT_ATTR(event, "config:0-31"), |
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NULL, |
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}; |
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static const struct attribute_group dsu_pmu_format_attr_group = { |
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.name = "format", |
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.attrs = dsu_pmu_format_attrs, |
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}; |
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static struct attribute *dsu_pmu_event_attrs[] = { |
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DSU_EVENT_ATTR(cycles, 0x11), |
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DSU_EVENT_ATTR(bus_access, 0x19), |
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DSU_EVENT_ATTR(memory_error, 0x1a), |
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DSU_EVENT_ATTR(bus_cycles, 0x1d), |
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DSU_EVENT_ATTR(l3d_cache_allocate, 0x29), |
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DSU_EVENT_ATTR(l3d_cache_refill, 0x2a), |
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DSU_EVENT_ATTR(l3d_cache, 0x2b), |
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DSU_EVENT_ATTR(l3d_cache_wb, 0x2c), |
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NULL, |
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}; |
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static umode_t |
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dsu_pmu_event_attr_is_visible(struct kobject *kobj, struct attribute *attr, |
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int unused) |
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{ |
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struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); |
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struct dsu_pmu *dsu_pmu = to_dsu_pmu(pmu); |
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struct dev_ext_attribute *eattr = container_of(attr, |
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struct dev_ext_attribute, attr.attr); |
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unsigned long evt = (unsigned long)eattr->var; |
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return test_bit(evt, dsu_pmu->cpmceid_bitmap) ? attr->mode : 0; |
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} |
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static const struct attribute_group dsu_pmu_events_attr_group = { |
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.name = "events", |
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.attrs = dsu_pmu_event_attrs, |
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.is_visible = dsu_pmu_event_attr_is_visible, |
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}; |
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static struct attribute *dsu_pmu_cpumask_attrs[] = { |
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DSU_CPUMASK_ATTR(cpumask, DSU_ACTIVE_CPU_MASK), |
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DSU_CPUMASK_ATTR(associated_cpus, DSU_ASSOCIATED_CPU_MASK), |
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NULL, |
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}; |
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static const struct attribute_group dsu_pmu_cpumask_attr_group = { |
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.attrs = dsu_pmu_cpumask_attrs, |
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}; |
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static const struct attribute_group *dsu_pmu_attr_groups[] = { |
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&dsu_pmu_cpumask_attr_group, |
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&dsu_pmu_events_attr_group, |
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&dsu_pmu_format_attr_group, |
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NULL, |
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}; |
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static int dsu_pmu_get_online_cpu_any_but(struct dsu_pmu *dsu_pmu, int cpu) |
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{ |
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struct cpumask online_supported; |
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cpumask_and(&online_supported, |
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&dsu_pmu->associated_cpus, cpu_online_mask); |
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return cpumask_any_but(&online_supported, cpu); |
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} |
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static inline bool dsu_pmu_counter_valid(struct dsu_pmu *dsu_pmu, u32 idx) |
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{ |
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return (idx < dsu_pmu->num_counters) || |
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(idx == DSU_PMU_IDX_CYCLE_COUNTER); |
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} |
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static inline u64 dsu_pmu_read_counter(struct perf_event *event) |
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{ |
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u64 val; |
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unsigned long flags; |
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struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu); |
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int idx = event->hw.idx; |
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if (WARN_ON(!cpumask_test_cpu(smp_processor_id(), |
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&dsu_pmu->associated_cpus))) |
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return 0; |
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if (!dsu_pmu_counter_valid(dsu_pmu, idx)) { |
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dev_err(event->pmu->dev, |
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"Trying reading invalid counter %d\n", idx); |
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return 0; |
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} |
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raw_spin_lock_irqsave(&dsu_pmu->pmu_lock, flags); |
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if (idx == DSU_PMU_IDX_CYCLE_COUNTER) |
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val = __dsu_pmu_read_pmccntr(); |
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else |
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val = __dsu_pmu_read_counter(idx); |
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raw_spin_unlock_irqrestore(&dsu_pmu->pmu_lock, flags); |
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return val; |
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} |
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static void dsu_pmu_write_counter(struct perf_event *event, u64 val) |
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{ |
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unsigned long flags; |
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struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu); |
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int idx = event->hw.idx; |
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if (WARN_ON(!cpumask_test_cpu(smp_processor_id(), |
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&dsu_pmu->associated_cpus))) |
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return; |
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if (!dsu_pmu_counter_valid(dsu_pmu, idx)) { |
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dev_err(event->pmu->dev, |
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"writing to invalid counter %d\n", idx); |
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return; |
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} |
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raw_spin_lock_irqsave(&dsu_pmu->pmu_lock, flags); |
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if (idx == DSU_PMU_IDX_CYCLE_COUNTER) |
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__dsu_pmu_write_pmccntr(val); |
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else |
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__dsu_pmu_write_counter(idx, val); |
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raw_spin_unlock_irqrestore(&dsu_pmu->pmu_lock, flags); |
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} |
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static int dsu_pmu_get_event_idx(struct dsu_hw_events *hw_events, |
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struct perf_event *event) |
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{ |
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int idx; |
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unsigned long evtype = event->attr.config; |
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struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu); |
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unsigned long *used_mask = hw_events->used_mask; |
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if (evtype == DSU_PMU_EVT_CYCLES) { |
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if (test_and_set_bit(DSU_PMU_IDX_CYCLE_COUNTER, used_mask)) |
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return -EAGAIN; |
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return DSU_PMU_IDX_CYCLE_COUNTER; |
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} |
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idx = find_first_zero_bit(used_mask, dsu_pmu->num_counters); |
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if (idx >= dsu_pmu->num_counters) |
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return -EAGAIN; |
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set_bit(idx, hw_events->used_mask); |
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return idx; |
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} |
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static void dsu_pmu_enable_counter(struct dsu_pmu *dsu_pmu, int idx) |
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{ |
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__dsu_pmu_counter_interrupt_enable(idx); |
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__dsu_pmu_enable_counter(idx); |
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} |
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static void dsu_pmu_disable_counter(struct dsu_pmu *dsu_pmu, int idx) |
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{ |
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__dsu_pmu_disable_counter(idx); |
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__dsu_pmu_counter_interrupt_disable(idx); |
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} |
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static inline void dsu_pmu_set_event(struct dsu_pmu *dsu_pmu, |
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struct perf_event *event) |
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{ |
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int idx = event->hw.idx; |
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unsigned long flags; |
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if (!dsu_pmu_counter_valid(dsu_pmu, idx)) { |
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dev_err(event->pmu->dev, |
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"Trying to set invalid counter %d\n", idx); |
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return; |
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} |
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raw_spin_lock_irqsave(&dsu_pmu->pmu_lock, flags); |
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__dsu_pmu_set_event(idx, event->hw.config_base); |
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raw_spin_unlock_irqrestore(&dsu_pmu->pmu_lock, flags); |
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} |
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static void dsu_pmu_event_update(struct perf_event *event) |
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{ |
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struct hw_perf_event *hwc = &event->hw; |
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u64 delta, prev_count, new_count; |
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do { |
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/* We may also be called from the irq handler */ |
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prev_count = local64_read(&hwc->prev_count); |
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new_count = dsu_pmu_read_counter(event); |
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} while (local64_cmpxchg(&hwc->prev_count, prev_count, new_count) != |
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prev_count); |
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delta = (new_count - prev_count) & DSU_PMU_COUNTER_MASK(hwc->idx); |
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local64_add(delta, &event->count); |
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} |
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static void dsu_pmu_read(struct perf_event *event) |
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{ |
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dsu_pmu_event_update(event); |
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} |
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static inline u32 dsu_pmu_get_reset_overflow(void) |
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{ |
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return __dsu_pmu_get_reset_overflow(); |
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} |
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/** |
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* dsu_pmu_set_event_period: Set the period for the counter. |
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* |
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* All DSU PMU event counters, except the cycle counter are 32bit |
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* counters. To handle cases of extreme interrupt latency, we program |
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* the counter with half of the max count for the counters. |
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*/ |
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static void dsu_pmu_set_event_period(struct perf_event *event) |
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{ |
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int idx = event->hw.idx; |
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u64 val = DSU_PMU_COUNTER_MASK(idx) >> 1; |
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local64_set(&event->hw.prev_count, val); |
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dsu_pmu_write_counter(event, val); |
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} |
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static irqreturn_t dsu_pmu_handle_irq(int irq_num, void *dev) |
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{ |
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int i; |
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bool handled = false; |
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struct dsu_pmu *dsu_pmu = dev; |
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struct dsu_hw_events *hw_events = &dsu_pmu->hw_events; |
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unsigned long overflow; |
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overflow = dsu_pmu_get_reset_overflow(); |
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if (!overflow) |
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return IRQ_NONE; |
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for_each_set_bit(i, &overflow, DSU_PMU_MAX_HW_CNTRS) { |
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struct perf_event *event = hw_events->events[i]; |
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if (!event) |
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continue; |
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dsu_pmu_event_update(event); |
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dsu_pmu_set_event_period(event); |
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handled = true; |
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} |
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return IRQ_RETVAL(handled); |
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} |
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static void dsu_pmu_start(struct perf_event *event, int pmu_flags) |
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{ |
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struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu); |
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/* We always reprogram the counter */ |
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if (pmu_flags & PERF_EF_RELOAD) |
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WARN_ON(!(event->hw.state & PERF_HES_UPTODATE)); |
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dsu_pmu_set_event_period(event); |
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if (event->hw.idx != DSU_PMU_IDX_CYCLE_COUNTER) |
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dsu_pmu_set_event(dsu_pmu, event); |
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event->hw.state = 0; |
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dsu_pmu_enable_counter(dsu_pmu, event->hw.idx); |
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} |
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static void dsu_pmu_stop(struct perf_event *event, int pmu_flags) |
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{ |
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struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu); |
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if (event->hw.state & PERF_HES_STOPPED) |
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return; |
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dsu_pmu_disable_counter(dsu_pmu, event->hw.idx); |
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dsu_pmu_event_update(event); |
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event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
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} |
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static int dsu_pmu_add(struct perf_event *event, int flags) |
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{ |
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struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu); |
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struct dsu_hw_events *hw_events = &dsu_pmu->hw_events; |
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struct hw_perf_event *hwc = &event->hw; |
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int idx; |
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if (WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), |
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&dsu_pmu->associated_cpus))) |
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return -ENOENT; |
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idx = dsu_pmu_get_event_idx(hw_events, event); |
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if (idx < 0) |
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return idx; |
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hwc->idx = idx; |
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hw_events->events[idx] = event; |
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hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
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if (flags & PERF_EF_START) |
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dsu_pmu_start(event, PERF_EF_RELOAD); |
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perf_event_update_userpage(event); |
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return 0; |
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} |
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static void dsu_pmu_del(struct perf_event *event, int flags) |
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{ |
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struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu); |
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struct dsu_hw_events *hw_events = &dsu_pmu->hw_events; |
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struct hw_perf_event *hwc = &event->hw; |
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int idx = hwc->idx; |
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dsu_pmu_stop(event, PERF_EF_UPDATE); |
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hw_events->events[idx] = NULL; |
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clear_bit(idx, hw_events->used_mask); |
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perf_event_update_userpage(event); |
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} |
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static void dsu_pmu_enable(struct pmu *pmu) |
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{ |
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u32 pmcr; |
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unsigned long flags; |
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struct dsu_pmu *dsu_pmu = to_dsu_pmu(pmu); |
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/* If no counters are added, skip enabling the PMU */ |
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if (bitmap_empty(dsu_pmu->hw_events.used_mask, DSU_PMU_MAX_HW_CNTRS)) |
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return; |
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raw_spin_lock_irqsave(&dsu_pmu->pmu_lock, flags); |
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pmcr = __dsu_pmu_read_pmcr(); |
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pmcr |= CLUSTERPMCR_E; |
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__dsu_pmu_write_pmcr(pmcr); |
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raw_spin_unlock_irqrestore(&dsu_pmu->pmu_lock, flags); |
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} |
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static void dsu_pmu_disable(struct pmu *pmu) |
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{ |
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u32 pmcr; |
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unsigned long flags; |
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struct dsu_pmu *dsu_pmu = to_dsu_pmu(pmu); |
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raw_spin_lock_irqsave(&dsu_pmu->pmu_lock, flags); |
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pmcr = __dsu_pmu_read_pmcr(); |
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pmcr &= ~CLUSTERPMCR_E; |
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__dsu_pmu_write_pmcr(pmcr); |
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raw_spin_unlock_irqrestore(&dsu_pmu->pmu_lock, flags); |
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} |
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|
|
static bool dsu_pmu_validate_event(struct pmu *pmu, |
|
struct dsu_hw_events *hw_events, |
|
struct perf_event *event) |
|
{ |
|
if (is_software_event(event)) |
|
return true; |
|
/* Reject groups spanning multiple HW PMUs. */ |
|
if (event->pmu != pmu) |
|
return false; |
|
return dsu_pmu_get_event_idx(hw_events, event) >= 0; |
|
} |
|
|
|
/* |
|
* Make sure the group of events can be scheduled at once |
|
* on the PMU. |
|
*/ |
|
static bool dsu_pmu_validate_group(struct perf_event *event) |
|
{ |
|
struct perf_event *sibling, *leader = event->group_leader; |
|
struct dsu_hw_events fake_hw; |
|
|
|
if (event->group_leader == event) |
|
return true; |
|
|
|
memset(fake_hw.used_mask, 0, sizeof(fake_hw.used_mask)); |
|
if (!dsu_pmu_validate_event(event->pmu, &fake_hw, leader)) |
|
return false; |
|
for_each_sibling_event(sibling, leader) { |
|
if (!dsu_pmu_validate_event(event->pmu, &fake_hw, sibling)) |
|
return false; |
|
} |
|
return dsu_pmu_validate_event(event->pmu, &fake_hw, event); |
|
} |
|
|
|
static int dsu_pmu_event_init(struct perf_event *event) |
|
{ |
|
struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu); |
|
|
|
if (event->attr.type != event->pmu->type) |
|
return -ENOENT; |
|
|
|
/* We don't support sampling */ |
|
if (is_sampling_event(event)) { |
|
dev_dbg(dsu_pmu->pmu.dev, "Can't support sampling events\n"); |
|
return -EOPNOTSUPP; |
|
} |
|
|
|
/* We cannot support task bound events */ |
|
if (event->cpu < 0 || event->attach_state & PERF_ATTACH_TASK) { |
|
dev_dbg(dsu_pmu->pmu.dev, "Can't support per-task counters\n"); |
|
return -EINVAL; |
|
} |
|
|
|
if (has_branch_stack(event)) { |
|
dev_dbg(dsu_pmu->pmu.dev, "Can't support filtering\n"); |
|
return -EINVAL; |
|
} |
|
|
|
if (!cpumask_test_cpu(event->cpu, &dsu_pmu->associated_cpus)) { |
|
dev_dbg(dsu_pmu->pmu.dev, |
|
"Requested cpu is not associated with the DSU\n"); |
|
return -EINVAL; |
|
} |
|
/* |
|
* Choose the current active CPU to read the events. We don't want |
|
* to migrate the event contexts, irq handling etc to the requested |
|
* CPU. As long as the requested CPU is within the same DSU, we |
|
* are fine. |
|
*/ |
|
event->cpu = cpumask_first(&dsu_pmu->active_cpu); |
|
if (event->cpu >= nr_cpu_ids) |
|
return -EINVAL; |
|
if (!dsu_pmu_validate_group(event)) |
|
return -EINVAL; |
|
|
|
event->hw.config_base = event->attr.config; |
|
return 0; |
|
} |
|
|
|
static struct dsu_pmu *dsu_pmu_alloc(struct platform_device *pdev) |
|
{ |
|
struct dsu_pmu *dsu_pmu; |
|
|
|
dsu_pmu = devm_kzalloc(&pdev->dev, sizeof(*dsu_pmu), GFP_KERNEL); |
|
if (!dsu_pmu) |
|
return ERR_PTR(-ENOMEM); |
|
|
|
raw_spin_lock_init(&dsu_pmu->pmu_lock); |
|
/* |
|
* Initialise the number of counters to -1, until we probe |
|
* the real number on a connected CPU. |
|
*/ |
|
dsu_pmu->num_counters = -1; |
|
return dsu_pmu; |
|
} |
|
|
|
/** |
|
* dsu_pmu_dt_get_cpus: Get the list of CPUs in the cluster |
|
* from device tree. |
|
*/ |
|
static int dsu_pmu_dt_get_cpus(struct device *dev, cpumask_t *mask) |
|
{ |
|
int i = 0, n, cpu; |
|
struct device_node *cpu_node; |
|
|
|
n = of_count_phandle_with_args(dev->of_node, "cpus", NULL); |
|
if (n <= 0) |
|
return -ENODEV; |
|
for (; i < n; i++) { |
|
cpu_node = of_parse_phandle(dev->of_node, "cpus", i); |
|
if (!cpu_node) |
|
break; |
|
cpu = of_cpu_node_to_id(cpu_node); |
|
of_node_put(cpu_node); |
|
/* |
|
* We have to ignore the failures here and continue scanning |
|
* the list to handle cases where the nr_cpus could be capped |
|
* in the running kernel. |
|
*/ |
|
if (cpu < 0) |
|
continue; |
|
cpumask_set_cpu(cpu, mask); |
|
} |
|
return 0; |
|
} |
|
|
|
/** |
|
* dsu_pmu_acpi_get_cpus: Get the list of CPUs in the cluster |
|
* from ACPI. |
|
*/ |
|
static int dsu_pmu_acpi_get_cpus(struct device *dev, cpumask_t *mask) |
|
{ |
|
#ifdef CONFIG_ACPI |
|
int cpu; |
|
|
|
/* |
|
* A dsu pmu node is inside a cluster parent node along with cpu nodes. |
|
* We need to find out all cpus that have the same parent with this pmu. |
|
*/ |
|
for_each_possible_cpu(cpu) { |
|
struct acpi_device *acpi_dev; |
|
struct device *cpu_dev = get_cpu_device(cpu); |
|
|
|
if (!cpu_dev) |
|
continue; |
|
|
|
acpi_dev = ACPI_COMPANION(cpu_dev); |
|
if (acpi_dev && |
|
acpi_dev->parent == ACPI_COMPANION(dev)->parent) |
|
cpumask_set_cpu(cpu, mask); |
|
} |
|
#endif |
|
|
|
return 0; |
|
} |
|
|
|
/* |
|
* dsu_pmu_probe_pmu: Probe the PMU details on a CPU in the cluster. |
|
*/ |
|
static void dsu_pmu_probe_pmu(struct dsu_pmu *dsu_pmu) |
|
{ |
|
u64 num_counters; |
|
u32 cpmceid[2]; |
|
|
|
num_counters = (__dsu_pmu_read_pmcr() >> CLUSTERPMCR_N_SHIFT) & |
|
CLUSTERPMCR_N_MASK; |
|
/* We can only support up to 31 independent counters */ |
|
if (WARN_ON(num_counters > 31)) |
|
num_counters = 31; |
|
dsu_pmu->num_counters = num_counters; |
|
if (!dsu_pmu->num_counters) |
|
return; |
|
cpmceid[0] = __dsu_pmu_read_pmceid(0); |
|
cpmceid[1] = __dsu_pmu_read_pmceid(1); |
|
bitmap_from_arr32(dsu_pmu->cpmceid_bitmap, cpmceid, |
|
DSU_PMU_MAX_COMMON_EVENTS); |
|
} |
|
|
|
static void dsu_pmu_set_active_cpu(int cpu, struct dsu_pmu *dsu_pmu) |
|
{ |
|
cpumask_set_cpu(cpu, &dsu_pmu->active_cpu); |
|
if (irq_set_affinity(dsu_pmu->irq, &dsu_pmu->active_cpu)) |
|
pr_warn("Failed to set irq affinity to %d\n", cpu); |
|
} |
|
|
|
/* |
|
* dsu_pmu_init_pmu: Initialise the DSU PMU configurations if |
|
* we haven't done it already. |
|
*/ |
|
static void dsu_pmu_init_pmu(struct dsu_pmu *dsu_pmu) |
|
{ |
|
if (dsu_pmu->num_counters == -1) |
|
dsu_pmu_probe_pmu(dsu_pmu); |
|
/* Reset the interrupt overflow mask */ |
|
dsu_pmu_get_reset_overflow(); |
|
} |
|
|
|
static int dsu_pmu_device_probe(struct platform_device *pdev) |
|
{ |
|
int irq, rc; |
|
struct dsu_pmu *dsu_pmu; |
|
struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev); |
|
char *name; |
|
static atomic_t pmu_idx = ATOMIC_INIT(-1); |
|
|
|
dsu_pmu = dsu_pmu_alloc(pdev); |
|
if (IS_ERR(dsu_pmu)) |
|
return PTR_ERR(dsu_pmu); |
|
|
|
if (is_of_node(fwnode)) |
|
rc = dsu_pmu_dt_get_cpus(&pdev->dev, &dsu_pmu->associated_cpus); |
|
else if (is_acpi_device_node(fwnode)) |
|
rc = dsu_pmu_acpi_get_cpus(&pdev->dev, &dsu_pmu->associated_cpus); |
|
else |
|
return -ENOENT; |
|
|
|
if (rc) { |
|
dev_warn(&pdev->dev, "Failed to parse the CPUs\n"); |
|
return rc; |
|
} |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) |
|
return -EINVAL; |
|
|
|
name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_%d", |
|
PMUNAME, atomic_inc_return(&pmu_idx)); |
|
if (!name) |
|
return -ENOMEM; |
|
rc = devm_request_irq(&pdev->dev, irq, dsu_pmu_handle_irq, |
|
IRQF_NOBALANCING, name, dsu_pmu); |
|
if (rc) { |
|
dev_warn(&pdev->dev, "Failed to request IRQ %d\n", irq); |
|
return rc; |
|
} |
|
|
|
dsu_pmu->irq = irq; |
|
platform_set_drvdata(pdev, dsu_pmu); |
|
rc = cpuhp_state_add_instance(dsu_pmu_cpuhp_state, |
|
&dsu_pmu->cpuhp_node); |
|
if (rc) |
|
return rc; |
|
|
|
dsu_pmu->pmu = (struct pmu) { |
|
.task_ctx_nr = perf_invalid_context, |
|
.module = THIS_MODULE, |
|
.pmu_enable = dsu_pmu_enable, |
|
.pmu_disable = dsu_pmu_disable, |
|
.event_init = dsu_pmu_event_init, |
|
.add = dsu_pmu_add, |
|
.del = dsu_pmu_del, |
|
.start = dsu_pmu_start, |
|
.stop = dsu_pmu_stop, |
|
.read = dsu_pmu_read, |
|
|
|
.attr_groups = dsu_pmu_attr_groups, |
|
.capabilities = PERF_PMU_CAP_NO_EXCLUDE, |
|
}; |
|
|
|
rc = perf_pmu_register(&dsu_pmu->pmu, name, -1); |
|
if (rc) { |
|
cpuhp_state_remove_instance(dsu_pmu_cpuhp_state, |
|
&dsu_pmu->cpuhp_node); |
|
} |
|
|
|
return rc; |
|
} |
|
|
|
static int dsu_pmu_device_remove(struct platform_device *pdev) |
|
{ |
|
struct dsu_pmu *dsu_pmu = platform_get_drvdata(pdev); |
|
|
|
perf_pmu_unregister(&dsu_pmu->pmu); |
|
cpuhp_state_remove_instance(dsu_pmu_cpuhp_state, &dsu_pmu->cpuhp_node); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id dsu_pmu_of_match[] = { |
|
{ .compatible = "arm,dsu-pmu", }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, dsu_pmu_of_match); |
|
|
|
#ifdef CONFIG_ACPI |
|
static const struct acpi_device_id dsu_pmu_acpi_match[] = { |
|
{ "ARMHD500", 0}, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(acpi, dsu_pmu_acpi_match); |
|
#endif |
|
|
|
static struct platform_driver dsu_pmu_driver = { |
|
.driver = { |
|
.name = DRVNAME, |
|
.of_match_table = of_match_ptr(dsu_pmu_of_match), |
|
.acpi_match_table = ACPI_PTR(dsu_pmu_acpi_match), |
|
.suppress_bind_attrs = true, |
|
}, |
|
.probe = dsu_pmu_device_probe, |
|
.remove = dsu_pmu_device_remove, |
|
}; |
|
|
|
static int dsu_pmu_cpu_online(unsigned int cpu, struct hlist_node *node) |
|
{ |
|
struct dsu_pmu *dsu_pmu = hlist_entry_safe(node, struct dsu_pmu, |
|
cpuhp_node); |
|
|
|
if (!cpumask_test_cpu(cpu, &dsu_pmu->associated_cpus)) |
|
return 0; |
|
|
|
/* If the PMU is already managed, there is nothing to do */ |
|
if (!cpumask_empty(&dsu_pmu->active_cpu)) |
|
return 0; |
|
|
|
dsu_pmu_init_pmu(dsu_pmu); |
|
dsu_pmu_set_active_cpu(cpu, dsu_pmu); |
|
|
|
return 0; |
|
} |
|
|
|
static int dsu_pmu_cpu_teardown(unsigned int cpu, struct hlist_node *node) |
|
{ |
|
int dst; |
|
struct dsu_pmu *dsu_pmu = hlist_entry_safe(node, struct dsu_pmu, |
|
cpuhp_node); |
|
|
|
if (!cpumask_test_and_clear_cpu(cpu, &dsu_pmu->active_cpu)) |
|
return 0; |
|
|
|
dst = dsu_pmu_get_online_cpu_any_but(dsu_pmu, cpu); |
|
/* If there are no active CPUs in the DSU, leave IRQ disabled */ |
|
if (dst >= nr_cpu_ids) |
|
return 0; |
|
|
|
perf_pmu_migrate_context(&dsu_pmu->pmu, cpu, dst); |
|
dsu_pmu_set_active_cpu(dst, dsu_pmu); |
|
|
|
return 0; |
|
} |
|
|
|
static int __init dsu_pmu_init(void) |
|
{ |
|
int ret; |
|
|
|
ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, |
|
DRVNAME, |
|
dsu_pmu_cpu_online, |
|
dsu_pmu_cpu_teardown); |
|
if (ret < 0) |
|
return ret; |
|
dsu_pmu_cpuhp_state = ret; |
|
return platform_driver_register(&dsu_pmu_driver); |
|
} |
|
|
|
static void __exit dsu_pmu_exit(void) |
|
{ |
|
platform_driver_unregister(&dsu_pmu_driver); |
|
cpuhp_remove_multi_state(dsu_pmu_cpuhp_state); |
|
} |
|
|
|
module_init(dsu_pmu_init); |
|
module_exit(dsu_pmu_exit); |
|
|
|
MODULE_DESCRIPTION("Perf driver for ARM DynamIQ Shared Unit"); |
|
MODULE_AUTHOR("Suzuki K Poulose <[email protected]>"); |
|
MODULE_LICENSE("GPL v2");
|
|
|