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749 lines
21 KiB
749 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* ARM DMC-620 memory controller PMU driver |
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* |
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* Copyright (C) 2020 Ampere Computing LLC. |
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*/ |
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|
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#define DMC620_PMUNAME "arm_dmc620" |
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#define DMC620_DRVNAME DMC620_PMUNAME "_pmu" |
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#define pr_fmt(fmt) DMC620_DRVNAME ": " fmt |
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#include <linux/acpi.h> |
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#include <linux/bitfield.h> |
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#include <linux/bitops.h> |
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#include <linux/cpuhotplug.h> |
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#include <linux/cpumask.h> |
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#include <linux/device.h> |
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#include <linux/errno.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/kernel.h> |
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#include <linux/list.h> |
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#include <linux/module.h> |
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#include <linux/mutex.h> |
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#include <linux/perf_event.h> |
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#include <linux/platform_device.h> |
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#include <linux/printk.h> |
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#include <linux/rculist.h> |
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#include <linux/refcount.h> |
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#define DMC620_PA_SHIFT 12 |
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#define DMC620_CNT_INIT 0x80000000 |
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#define DMC620_CNT_MAX_PERIOD 0xffffffff |
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#define DMC620_PMU_CLKDIV2_MAX_COUNTERS 8 |
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#define DMC620_PMU_CLK_MAX_COUNTERS 2 |
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#define DMC620_PMU_MAX_COUNTERS \ |
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(DMC620_PMU_CLKDIV2_MAX_COUNTERS + DMC620_PMU_CLK_MAX_COUNTERS) |
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/* |
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* The PMU registers start at 0xA00 in the DMC-620 memory map, and these |
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* offsets are relative to that base. |
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* |
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* Each counter has a group of control/value registers, and the |
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* DMC620_PMU_COUNTERn offsets are within a counter group. |
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* |
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* The counter registers groups start at 0xA10. |
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*/ |
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#define DMC620_PMU_OVERFLOW_STATUS_CLKDIV2 0x8 |
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#define DMC620_PMU_OVERFLOW_STATUS_CLKDIV2_MASK \ |
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(DMC620_PMU_CLKDIV2_MAX_COUNTERS - 1) |
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#define DMC620_PMU_OVERFLOW_STATUS_CLK 0xC |
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#define DMC620_PMU_OVERFLOW_STATUS_CLK_MASK \ |
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(DMC620_PMU_CLK_MAX_COUNTERS - 1) |
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#define DMC620_PMU_COUNTERS_BASE 0x10 |
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#define DMC620_PMU_COUNTERn_MASK_31_00 0x0 |
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#define DMC620_PMU_COUNTERn_MASK_63_32 0x4 |
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#define DMC620_PMU_COUNTERn_MATCH_31_00 0x8 |
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#define DMC620_PMU_COUNTERn_MATCH_63_32 0xC |
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#define DMC620_PMU_COUNTERn_CONTROL 0x10 |
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#define DMC620_PMU_COUNTERn_CONTROL_ENABLE BIT(0) |
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#define DMC620_PMU_COUNTERn_CONTROL_INVERT BIT(1) |
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#define DMC620_PMU_COUNTERn_CONTROL_EVENT_MUX GENMASK(6, 2) |
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#define DMC620_PMU_COUNTERn_CONTROL_INCR_MUX GENMASK(8, 7) |
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#define DMC620_PMU_COUNTERn_VALUE 0x20 |
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/* Offset of the registers for a given counter, relative to 0xA00 */ |
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#define DMC620_PMU_COUNTERn_OFFSET(n) \ |
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(DMC620_PMU_COUNTERS_BASE + 0x28 * (n)) |
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static LIST_HEAD(dmc620_pmu_irqs); |
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static DEFINE_MUTEX(dmc620_pmu_irqs_lock); |
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struct dmc620_pmu_irq { |
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struct hlist_node node; |
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struct list_head pmus_node; |
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struct list_head irqs_node; |
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refcount_t refcount; |
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unsigned int irq_num; |
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unsigned int cpu; |
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}; |
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struct dmc620_pmu { |
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struct pmu pmu; |
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void __iomem *base; |
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struct dmc620_pmu_irq *irq; |
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struct list_head pmus_node; |
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/* |
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* We put all clkdiv2 and clk counters to a same array. |
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* The first DMC620_PMU_CLKDIV2_MAX_COUNTERS bits belong to |
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* clkdiv2 counters, the last DMC620_PMU_CLK_MAX_COUNTERS |
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* belong to clk counters. |
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*/ |
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DECLARE_BITMAP(used_mask, DMC620_PMU_MAX_COUNTERS); |
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struct perf_event *events[DMC620_PMU_MAX_COUNTERS]; |
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}; |
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#define to_dmc620_pmu(p) (container_of(p, struct dmc620_pmu, pmu)) |
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static int cpuhp_state_num; |
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struct dmc620_pmu_event_attr { |
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struct device_attribute attr; |
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u8 clkdiv2; |
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u8 eventid; |
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}; |
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static ssize_t |
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dmc620_pmu_event_show(struct device *dev, |
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struct device_attribute *attr, char *page) |
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{ |
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struct dmc620_pmu_event_attr *eattr; |
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eattr = container_of(attr, typeof(*eattr), attr); |
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return sysfs_emit(page, "event=0x%x,clkdiv2=0x%x\n", eattr->eventid, eattr->clkdiv2); |
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} |
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#define DMC620_PMU_EVENT_ATTR(_name, _eventid, _clkdiv2) \ |
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(&((struct dmc620_pmu_event_attr[]) {{ \ |
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.attr = __ATTR(_name, 0444, dmc620_pmu_event_show, NULL), \ |
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.clkdiv2 = _clkdiv2, \ |
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.eventid = _eventid, \ |
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}})[0].attr.attr) |
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static struct attribute *dmc620_pmu_events_attrs[] = { |
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/* clkdiv2 events list */ |
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DMC620_PMU_EVENT_ATTR(clkdiv2_cycle_count, 0x0, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_allocate, 0x1, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_queue_depth, 0x2, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_waiting_for_wr_data, 0x3, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_read_backlog, 0x4, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_waiting_for_mi, 0x5, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_hazard_resolution, 0x6, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_enqueue, 0x7, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_arbitrate, 0x8, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_lrank_turnaround_activate, 0x9, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_prank_turnaround_activate, 0xa, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_read_depth, 0xb, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_write_depth, 0xc, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_highigh_qos_depth, 0xd, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_high_qos_depth, 0xe, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_medium_qos_depth, 0xf, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_low_qos_depth, 0x10, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_activate, 0x11, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_rdwr, 0x12, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_refresh, 0x13, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_training_request, 0x14, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_t_mac_tracker, 0x15, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_bk_fsm_tracker, 0x16, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_bk_open_tracker, 0x17, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_ranks_in_pwr_down, 0x18, 1), |
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DMC620_PMU_EVENT_ATTR(clkdiv2_ranks_in_sref, 0x19, 1), |
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|
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/* clk events list */ |
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DMC620_PMU_EVENT_ATTR(clk_cycle_count, 0x0, 0), |
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DMC620_PMU_EVENT_ATTR(clk_request, 0x1, 0), |
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DMC620_PMU_EVENT_ATTR(clk_upload_stall, 0x2, 0), |
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NULL, |
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}; |
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static const struct attribute_group dmc620_pmu_events_attr_group = { |
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.name = "events", |
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.attrs = dmc620_pmu_events_attrs, |
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}; |
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/* User ABI */ |
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#define ATTR_CFG_FLD_mask_CFG config |
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#define ATTR_CFG_FLD_mask_LO 0 |
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#define ATTR_CFG_FLD_mask_HI 44 |
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#define ATTR_CFG_FLD_match_CFG config1 |
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#define ATTR_CFG_FLD_match_LO 0 |
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#define ATTR_CFG_FLD_match_HI 44 |
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#define ATTR_CFG_FLD_invert_CFG config2 |
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#define ATTR_CFG_FLD_invert_LO 0 |
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#define ATTR_CFG_FLD_invert_HI 0 |
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#define ATTR_CFG_FLD_incr_CFG config2 |
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#define ATTR_CFG_FLD_incr_LO 1 |
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#define ATTR_CFG_FLD_incr_HI 2 |
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#define ATTR_CFG_FLD_event_CFG config2 |
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#define ATTR_CFG_FLD_event_LO 3 |
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#define ATTR_CFG_FLD_event_HI 8 |
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#define ATTR_CFG_FLD_clkdiv2_CFG config2 |
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#define ATTR_CFG_FLD_clkdiv2_LO 9 |
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#define ATTR_CFG_FLD_clkdiv2_HI 9 |
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#define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ |
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(lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi |
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#define _GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ |
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__GEN_PMU_FORMAT_ATTR(cfg, lo, hi) |
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#define GEN_PMU_FORMAT_ATTR(name) \ |
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PMU_FORMAT_ATTR(name, \ |
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_GEN_PMU_FORMAT_ATTR(ATTR_CFG_FLD_##name##_CFG, \ |
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ATTR_CFG_FLD_##name##_LO, \ |
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ATTR_CFG_FLD_##name##_HI)) |
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#define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi) \ |
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((((attr)->cfg) >> lo) & GENMASK_ULL(hi - lo, 0)) |
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#define ATTR_CFG_GET_FLD(attr, name) \ |
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_ATTR_CFG_GET_FLD(attr, \ |
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ATTR_CFG_FLD_##name##_CFG, \ |
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ATTR_CFG_FLD_##name##_LO, \ |
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ATTR_CFG_FLD_##name##_HI) |
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GEN_PMU_FORMAT_ATTR(mask); |
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GEN_PMU_FORMAT_ATTR(match); |
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GEN_PMU_FORMAT_ATTR(invert); |
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GEN_PMU_FORMAT_ATTR(incr); |
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GEN_PMU_FORMAT_ATTR(event); |
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GEN_PMU_FORMAT_ATTR(clkdiv2); |
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static struct attribute *dmc620_pmu_formats_attrs[] = { |
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&format_attr_mask.attr, |
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&format_attr_match.attr, |
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&format_attr_invert.attr, |
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&format_attr_incr.attr, |
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&format_attr_event.attr, |
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&format_attr_clkdiv2.attr, |
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NULL, |
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}; |
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static const struct attribute_group dmc620_pmu_format_attr_group = { |
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.name = "format", |
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.attrs = dmc620_pmu_formats_attrs, |
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}; |
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static const struct attribute_group *dmc620_pmu_attr_groups[] = { |
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&dmc620_pmu_events_attr_group, |
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&dmc620_pmu_format_attr_group, |
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NULL, |
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}; |
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static inline |
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u32 dmc620_pmu_creg_read(struct dmc620_pmu *dmc620_pmu, |
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unsigned int idx, unsigned int reg) |
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{ |
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return readl(dmc620_pmu->base + DMC620_PMU_COUNTERn_OFFSET(idx) + reg); |
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} |
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static inline |
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void dmc620_pmu_creg_write(struct dmc620_pmu *dmc620_pmu, |
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unsigned int idx, unsigned int reg, u32 val) |
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{ |
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writel(val, dmc620_pmu->base + DMC620_PMU_COUNTERn_OFFSET(idx) + reg); |
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} |
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static |
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unsigned int dmc620_event_to_counter_control(struct perf_event *event) |
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{ |
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struct perf_event_attr *attr = &event->attr; |
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unsigned int reg = 0; |
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reg |= FIELD_PREP(DMC620_PMU_COUNTERn_CONTROL_INVERT, |
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ATTR_CFG_GET_FLD(attr, invert)); |
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reg |= FIELD_PREP(DMC620_PMU_COUNTERn_CONTROL_EVENT_MUX, |
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ATTR_CFG_GET_FLD(attr, event)); |
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reg |= FIELD_PREP(DMC620_PMU_COUNTERn_CONTROL_INCR_MUX, |
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ATTR_CFG_GET_FLD(attr, incr)); |
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return reg; |
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} |
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static int dmc620_get_event_idx(struct perf_event *event) |
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{ |
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struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); |
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int idx, start_idx, end_idx; |
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if (ATTR_CFG_GET_FLD(&event->attr, clkdiv2)) { |
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start_idx = 0; |
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end_idx = DMC620_PMU_CLKDIV2_MAX_COUNTERS; |
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} else { |
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start_idx = DMC620_PMU_CLKDIV2_MAX_COUNTERS; |
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end_idx = DMC620_PMU_MAX_COUNTERS; |
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} |
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for (idx = start_idx; idx < end_idx; ++idx) { |
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if (!test_and_set_bit(idx, dmc620_pmu->used_mask)) |
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return idx; |
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} |
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|
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/* The counters are all in use. */ |
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return -EAGAIN; |
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} |
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static inline |
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u64 dmc620_pmu_read_counter(struct perf_event *event) |
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{ |
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struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); |
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return dmc620_pmu_creg_read(dmc620_pmu, |
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event->hw.idx, DMC620_PMU_COUNTERn_VALUE); |
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} |
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static void dmc620_pmu_event_update(struct perf_event *event) |
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{ |
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struct hw_perf_event *hwc = &event->hw; |
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u64 delta, prev_count, new_count; |
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do { |
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/* We may also be called from the irq handler */ |
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prev_count = local64_read(&hwc->prev_count); |
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new_count = dmc620_pmu_read_counter(event); |
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} while (local64_cmpxchg(&hwc->prev_count, |
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prev_count, new_count) != prev_count); |
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delta = (new_count - prev_count) & DMC620_CNT_MAX_PERIOD; |
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local64_add(delta, &event->count); |
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} |
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static void dmc620_pmu_event_set_period(struct perf_event *event) |
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{ |
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struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); |
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local64_set(&event->hw.prev_count, DMC620_CNT_INIT); |
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dmc620_pmu_creg_write(dmc620_pmu, |
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event->hw.idx, DMC620_PMU_COUNTERn_VALUE, DMC620_CNT_INIT); |
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} |
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static void dmc620_pmu_enable_counter(struct perf_event *event) |
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{ |
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struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); |
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u32 reg; |
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reg = dmc620_event_to_counter_control(event) | DMC620_PMU_COUNTERn_CONTROL_ENABLE; |
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dmc620_pmu_creg_write(dmc620_pmu, |
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event->hw.idx, DMC620_PMU_COUNTERn_CONTROL, reg); |
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} |
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static void dmc620_pmu_disable_counter(struct perf_event *event) |
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{ |
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struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); |
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dmc620_pmu_creg_write(dmc620_pmu, |
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event->hw.idx, DMC620_PMU_COUNTERn_CONTROL, 0); |
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} |
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static irqreturn_t dmc620_pmu_handle_irq(int irq_num, void *data) |
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{ |
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struct dmc620_pmu_irq *irq = data; |
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struct dmc620_pmu *dmc620_pmu; |
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irqreturn_t ret = IRQ_NONE; |
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rcu_read_lock(); |
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list_for_each_entry_rcu(dmc620_pmu, &irq->pmus_node, pmus_node) { |
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unsigned long status; |
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struct perf_event *event; |
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unsigned int idx; |
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|
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/* |
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* HW doesn't provide a control to atomically disable all counters. |
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* To prevent race condition (overflow happens while clearing status register), |
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* disable all events before continuing |
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*/ |
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for (idx = 0; idx < DMC620_PMU_MAX_COUNTERS; idx++) { |
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event = dmc620_pmu->events[idx]; |
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if (!event) |
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continue; |
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dmc620_pmu_disable_counter(event); |
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} |
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status = readl(dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLKDIV2); |
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status |= (readl(dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLK) << |
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DMC620_PMU_CLKDIV2_MAX_COUNTERS); |
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if (status) { |
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for_each_set_bit(idx, &status, |
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DMC620_PMU_MAX_COUNTERS) { |
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event = dmc620_pmu->events[idx]; |
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if (WARN_ON_ONCE(!event)) |
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continue; |
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dmc620_pmu_event_update(event); |
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dmc620_pmu_event_set_period(event); |
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} |
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|
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if (status & DMC620_PMU_OVERFLOW_STATUS_CLKDIV2_MASK) |
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writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLKDIV2); |
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|
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if ((status >> DMC620_PMU_CLKDIV2_MAX_COUNTERS) & |
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DMC620_PMU_OVERFLOW_STATUS_CLK_MASK) |
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writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLK); |
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} |
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|
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for (idx = 0; idx < DMC620_PMU_MAX_COUNTERS; idx++) { |
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event = dmc620_pmu->events[idx]; |
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if (!event) |
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continue; |
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if (!(event->hw.state & PERF_HES_STOPPED)) |
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dmc620_pmu_enable_counter(event); |
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} |
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|
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ret = IRQ_HANDLED; |
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} |
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rcu_read_unlock(); |
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|
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return ret; |
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} |
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|
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static struct dmc620_pmu_irq *__dmc620_pmu_get_irq(int irq_num) |
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{ |
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struct dmc620_pmu_irq *irq; |
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int ret; |
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|
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list_for_each_entry(irq, &dmc620_pmu_irqs, irqs_node) |
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if (irq->irq_num == irq_num && refcount_inc_not_zero(&irq->refcount)) |
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return irq; |
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irq = kzalloc(sizeof(*irq), GFP_KERNEL); |
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if (!irq) |
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return ERR_PTR(-ENOMEM); |
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|
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INIT_LIST_HEAD(&irq->pmus_node); |
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|
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/* Pick one CPU to be the preferred one to use */ |
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irq->cpu = raw_smp_processor_id(); |
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refcount_set(&irq->refcount, 1); |
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|
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ret = request_irq(irq_num, dmc620_pmu_handle_irq, |
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IRQF_NOBALANCING | IRQF_NO_THREAD, |
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"dmc620-pmu", irq); |
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if (ret) |
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goto out_free_aff; |
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|
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ret = irq_set_affinity(irq_num, cpumask_of(irq->cpu)); |
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if (ret) |
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goto out_free_irq; |
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|
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ret = cpuhp_state_add_instance_nocalls(cpuhp_state_num, &irq->node); |
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if (ret) |
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goto out_free_irq; |
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|
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irq->irq_num = irq_num; |
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list_add(&irq->irqs_node, &dmc620_pmu_irqs); |
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|
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return irq; |
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out_free_irq: |
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free_irq(irq_num, irq); |
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out_free_aff: |
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kfree(irq); |
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return ERR_PTR(ret); |
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} |
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|
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static int dmc620_pmu_get_irq(struct dmc620_pmu *dmc620_pmu, int irq_num) |
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{ |
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struct dmc620_pmu_irq *irq; |
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|
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mutex_lock(&dmc620_pmu_irqs_lock); |
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irq = __dmc620_pmu_get_irq(irq_num); |
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mutex_unlock(&dmc620_pmu_irqs_lock); |
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|
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if (IS_ERR(irq)) |
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return PTR_ERR(irq); |
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dmc620_pmu->irq = irq; |
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mutex_lock(&dmc620_pmu_irqs_lock); |
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list_add_rcu(&dmc620_pmu->pmus_node, &irq->pmus_node); |
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mutex_unlock(&dmc620_pmu_irqs_lock); |
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|
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return 0; |
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} |
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|
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static void dmc620_pmu_put_irq(struct dmc620_pmu *dmc620_pmu) |
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{ |
|
struct dmc620_pmu_irq *irq = dmc620_pmu->irq; |
|
|
|
mutex_lock(&dmc620_pmu_irqs_lock); |
|
list_del_rcu(&dmc620_pmu->pmus_node); |
|
|
|
if (!refcount_dec_and_test(&irq->refcount)) { |
|
mutex_unlock(&dmc620_pmu_irqs_lock); |
|
return; |
|
} |
|
|
|
list_del(&irq->irqs_node); |
|
mutex_unlock(&dmc620_pmu_irqs_lock); |
|
|
|
free_irq(irq->irq_num, irq); |
|
cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &irq->node); |
|
kfree(irq); |
|
} |
|
|
|
static int dmc620_pmu_event_init(struct perf_event *event) |
|
{ |
|
struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); |
|
struct hw_perf_event *hwc = &event->hw; |
|
struct perf_event *sibling; |
|
|
|
if (event->attr.type != event->pmu->type) |
|
return -ENOENT; |
|
|
|
/* |
|
* DMC 620 PMUs are shared across all cpus and cannot |
|
* support task bound and sampling events. |
|
*/ |
|
if (is_sampling_event(event) || |
|
event->attach_state & PERF_ATTACH_TASK) { |
|
dev_dbg(dmc620_pmu->pmu.dev, |
|
"Can't support per-task counters\n"); |
|
return -EOPNOTSUPP; |
|
} |
|
|
|
/* |
|
* Many perf core operations (eg. events rotation) operate on a |
|
* single CPU context. This is obvious for CPU PMUs, where one |
|
* expects the same sets of events being observed on all CPUs, |
|
* but can lead to issues for off-core PMUs, where each |
|
* event could be theoretically assigned to a different CPU. To |
|
* mitigate this, we enforce CPU assignment to one, selected |
|
* processor. |
|
*/ |
|
event->cpu = dmc620_pmu->irq->cpu; |
|
if (event->cpu < 0) |
|
return -EINVAL; |
|
|
|
/* |
|
* We can't atomically disable all HW counters so only one event allowed, |
|
* although software events are acceptable. |
|
*/ |
|
if (event->group_leader != event && |
|
!is_software_event(event->group_leader)) |
|
return -EINVAL; |
|
|
|
for_each_sibling_event(sibling, event->group_leader) { |
|
if (sibling != event && |
|
!is_software_event(sibling)) |
|
return -EINVAL; |
|
} |
|
|
|
hwc->idx = -1; |
|
return 0; |
|
} |
|
|
|
static void dmc620_pmu_read(struct perf_event *event) |
|
{ |
|
dmc620_pmu_event_update(event); |
|
} |
|
|
|
static void dmc620_pmu_start(struct perf_event *event, int flags) |
|
{ |
|
event->hw.state = 0; |
|
dmc620_pmu_event_set_period(event); |
|
dmc620_pmu_enable_counter(event); |
|
} |
|
|
|
static void dmc620_pmu_stop(struct perf_event *event, int flags) |
|
{ |
|
if (event->hw.state & PERF_HES_STOPPED) |
|
return; |
|
|
|
dmc620_pmu_disable_counter(event); |
|
dmc620_pmu_event_update(event); |
|
event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
|
} |
|
|
|
static int dmc620_pmu_add(struct perf_event *event, int flags) |
|
{ |
|
struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); |
|
struct perf_event_attr *attr = &event->attr; |
|
struct hw_perf_event *hwc = &event->hw; |
|
int idx; |
|
u64 reg; |
|
|
|
idx = dmc620_get_event_idx(event); |
|
if (idx < 0) |
|
return idx; |
|
|
|
hwc->idx = idx; |
|
dmc620_pmu->events[idx] = event; |
|
hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
|
|
|
reg = ATTR_CFG_GET_FLD(attr, mask); |
|
dmc620_pmu_creg_write(dmc620_pmu, |
|
idx, DMC620_PMU_COUNTERn_MASK_31_00, lower_32_bits(reg)); |
|
dmc620_pmu_creg_write(dmc620_pmu, |
|
idx, DMC620_PMU_COUNTERn_MASK_63_32, upper_32_bits(reg)); |
|
|
|
reg = ATTR_CFG_GET_FLD(attr, match); |
|
dmc620_pmu_creg_write(dmc620_pmu, |
|
idx, DMC620_PMU_COUNTERn_MATCH_31_00, lower_32_bits(reg)); |
|
dmc620_pmu_creg_write(dmc620_pmu, |
|
idx, DMC620_PMU_COUNTERn_MATCH_63_32, upper_32_bits(reg)); |
|
|
|
if (flags & PERF_EF_START) |
|
dmc620_pmu_start(event, PERF_EF_RELOAD); |
|
|
|
perf_event_update_userpage(event); |
|
return 0; |
|
} |
|
|
|
static void dmc620_pmu_del(struct perf_event *event, int flags) |
|
{ |
|
struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); |
|
struct hw_perf_event *hwc = &event->hw; |
|
int idx = hwc->idx; |
|
|
|
dmc620_pmu_stop(event, PERF_EF_UPDATE); |
|
dmc620_pmu->events[idx] = NULL; |
|
clear_bit(idx, dmc620_pmu->used_mask); |
|
perf_event_update_userpage(event); |
|
} |
|
|
|
static int dmc620_pmu_cpu_teardown(unsigned int cpu, |
|
struct hlist_node *node) |
|
{ |
|
struct dmc620_pmu_irq *irq; |
|
struct dmc620_pmu *dmc620_pmu; |
|
unsigned int target; |
|
|
|
irq = hlist_entry_safe(node, struct dmc620_pmu_irq, node); |
|
if (cpu != irq->cpu) |
|
return 0; |
|
|
|
target = cpumask_any_but(cpu_online_mask, cpu); |
|
if (target >= nr_cpu_ids) |
|
return 0; |
|
|
|
/* We're only reading, but this isn't the place to be involving RCU */ |
|
mutex_lock(&dmc620_pmu_irqs_lock); |
|
list_for_each_entry(dmc620_pmu, &irq->pmus_node, pmus_node) |
|
perf_pmu_migrate_context(&dmc620_pmu->pmu, irq->cpu, target); |
|
mutex_unlock(&dmc620_pmu_irqs_lock); |
|
|
|
WARN_ON(irq_set_affinity(irq->irq_num, cpumask_of(target))); |
|
irq->cpu = target; |
|
|
|
return 0; |
|
} |
|
|
|
static int dmc620_pmu_device_probe(struct platform_device *pdev) |
|
{ |
|
struct dmc620_pmu *dmc620_pmu; |
|
struct resource *res; |
|
char *name; |
|
int irq_num; |
|
int i, ret; |
|
|
|
dmc620_pmu = devm_kzalloc(&pdev->dev, |
|
sizeof(struct dmc620_pmu), GFP_KERNEL); |
|
if (!dmc620_pmu) |
|
return -ENOMEM; |
|
|
|
platform_set_drvdata(pdev, dmc620_pmu); |
|
|
|
dmc620_pmu->pmu = (struct pmu) { |
|
.module = THIS_MODULE, |
|
.capabilities = PERF_PMU_CAP_NO_EXCLUDE, |
|
.task_ctx_nr = perf_invalid_context, |
|
.event_init = dmc620_pmu_event_init, |
|
.add = dmc620_pmu_add, |
|
.del = dmc620_pmu_del, |
|
.start = dmc620_pmu_start, |
|
.stop = dmc620_pmu_stop, |
|
.read = dmc620_pmu_read, |
|
.attr_groups = dmc620_pmu_attr_groups, |
|
}; |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
dmc620_pmu->base = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(dmc620_pmu->base)) |
|
return PTR_ERR(dmc620_pmu->base); |
|
|
|
/* Make sure device is reset before enabling interrupt */ |
|
for (i = 0; i < DMC620_PMU_MAX_COUNTERS; i++) |
|
dmc620_pmu_creg_write(dmc620_pmu, i, DMC620_PMU_COUNTERn_CONTROL, 0); |
|
writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLKDIV2); |
|
writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLK); |
|
|
|
irq_num = platform_get_irq(pdev, 0); |
|
if (irq_num < 0) |
|
return irq_num; |
|
|
|
ret = dmc620_pmu_get_irq(dmc620_pmu, irq_num); |
|
if (ret) |
|
return ret; |
|
|
|
name = devm_kasprintf(&pdev->dev, GFP_KERNEL, |
|
"%s_%llx", DMC620_PMUNAME, |
|
(u64)(res->start >> DMC620_PA_SHIFT)); |
|
if (!name) { |
|
dev_err(&pdev->dev, |
|
"Create name failed, PMU @%pa\n", &res->start); |
|
ret = -ENOMEM; |
|
goto out_teardown_dev; |
|
} |
|
|
|
ret = perf_pmu_register(&dmc620_pmu->pmu, name, -1); |
|
if (ret) |
|
goto out_teardown_dev; |
|
|
|
return 0; |
|
|
|
out_teardown_dev: |
|
dmc620_pmu_put_irq(dmc620_pmu); |
|
synchronize_rcu(); |
|
return ret; |
|
} |
|
|
|
static int dmc620_pmu_device_remove(struct platform_device *pdev) |
|
{ |
|
struct dmc620_pmu *dmc620_pmu = platform_get_drvdata(pdev); |
|
|
|
dmc620_pmu_put_irq(dmc620_pmu); |
|
|
|
/* perf will synchronise RCU before devres can free dmc620_pmu */ |
|
perf_pmu_unregister(&dmc620_pmu->pmu); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct acpi_device_id dmc620_acpi_match[] = { |
|
{ "ARMHD620", 0}, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(acpi, dmc620_acpi_match); |
|
static struct platform_driver dmc620_pmu_driver = { |
|
.driver = { |
|
.name = DMC620_DRVNAME, |
|
.acpi_match_table = dmc620_acpi_match, |
|
.suppress_bind_attrs = true, |
|
}, |
|
.probe = dmc620_pmu_device_probe, |
|
.remove = dmc620_pmu_device_remove, |
|
}; |
|
|
|
static int __init dmc620_pmu_init(void) |
|
{ |
|
cpuhp_state_num = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, |
|
DMC620_DRVNAME, |
|
NULL, |
|
dmc620_pmu_cpu_teardown); |
|
if (cpuhp_state_num < 0) |
|
return cpuhp_state_num; |
|
|
|
return platform_driver_register(&dmc620_pmu_driver); |
|
} |
|
|
|
static void __exit dmc620_pmu_exit(void) |
|
{ |
|
platform_driver_unregister(&dmc620_pmu_driver); |
|
cpuhp_remove_multi_state(cpuhp_state_num); |
|
} |
|
|
|
module_init(dmc620_pmu_init); |
|
module_exit(dmc620_pmu_exit); |
|
|
|
MODULE_DESCRIPTION("Perf driver for the ARM DMC-620 memory controller"); |
|
MODULE_AUTHOR("Tuan Phan <[email protected]"); |
|
MODULE_LICENSE("GPL v2");
|
|
|