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653 lines
18 KiB
653 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Rockchip AXI PCIe endpoint controller driver |
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* |
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* Copyright (c) 2018 Rockchip, Inc. |
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* |
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* Author: Shawn Lin <[email protected]> |
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* Simon Xue <[email protected]> |
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*/ |
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#include <linux/configfs.h> |
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#include <linux/delay.h> |
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#include <linux/kernel.h> |
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#include <linux/of.h> |
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#include <linux/pci-epc.h> |
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#include <linux/platform_device.h> |
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#include <linux/pci-epf.h> |
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#include <linux/sizes.h> |
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#include "pcie-rockchip.h" |
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/** |
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* struct rockchip_pcie_ep - private data for PCIe endpoint controller driver |
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* @rockchip: Rockchip PCIe controller |
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* @epc: PCI EPC device |
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* @max_regions: maximum number of regions supported by hardware |
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* @ob_region_map: bitmask of mapped outbound regions |
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* @ob_addr: base addresses in the AXI bus where the outbound regions start |
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* @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ |
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* dedicated outbound regions is mapped. |
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* @irq_cpu_addr: base address in the CPU space where a write access triggers |
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* the sending of a memory write (MSI) / normal message (legacy |
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* IRQ) TLP through the PCIe bus. |
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* @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ |
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* dedicated outbound region. |
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* @irq_pci_fn: the latest PCI function that has updated the mapping of |
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* the MSI/legacy IRQ dedicated outbound region. |
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* @irq_pending: bitmask of asserted legacy IRQs. |
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*/ |
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struct rockchip_pcie_ep { |
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struct rockchip_pcie rockchip; |
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struct pci_epc *epc; |
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u32 max_regions; |
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unsigned long ob_region_map; |
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phys_addr_t *ob_addr; |
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phys_addr_t irq_phys_addr; |
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void __iomem *irq_cpu_addr; |
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u64 irq_pci_addr; |
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u8 irq_pci_fn; |
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u8 irq_pending; |
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}; |
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static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip, |
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u32 region) |
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{ |
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rockchip_pcie_write(rockchip, 0, |
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(region)); |
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rockchip_pcie_write(rockchip, 0, |
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(region)); |
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rockchip_pcie_write(rockchip, 0, |
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ROCKCHIP_PCIE_AT_OB_REGION_DESC0(region)); |
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rockchip_pcie_write(rockchip, 0, |
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ROCKCHIP_PCIE_AT_OB_REGION_DESC1(region)); |
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rockchip_pcie_write(rockchip, 0, |
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ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(region)); |
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rockchip_pcie_write(rockchip, 0, |
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ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(region)); |
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} |
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static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, |
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u32 r, u32 type, u64 cpu_addr, |
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u64 pci_addr, size_t size) |
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{ |
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u64 sz = 1ULL << fls64(size - 1); |
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int num_pass_bits = ilog2(sz); |
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u32 addr0, addr1, desc0, desc1; |
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bool is_nor_msg = (type == AXI_WRAPPER_NOR_MSG); |
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/* The minimal region size is 1MB */ |
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if (num_pass_bits < 8) |
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num_pass_bits = 8; |
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cpu_addr -= rockchip->mem_res->start; |
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addr0 = ((is_nor_msg ? 0x10 : (num_pass_bits - 1)) & |
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PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | |
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(lower_32_bits(cpu_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); |
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addr1 = upper_32_bits(is_nor_msg ? cpu_addr : pci_addr); |
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desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | type; |
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desc1 = 0; |
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if (is_nor_msg) { |
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rockchip_pcie_write(rockchip, 0, |
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r)); |
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rockchip_pcie_write(rockchip, 0, |
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r)); |
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rockchip_pcie_write(rockchip, desc0, |
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ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); |
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rockchip_pcie_write(rockchip, desc1, |
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ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); |
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} else { |
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/* PCI bus address region */ |
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rockchip_pcie_write(rockchip, addr0, |
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r)); |
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rockchip_pcie_write(rockchip, addr1, |
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r)); |
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rockchip_pcie_write(rockchip, desc0, |
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ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); |
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rockchip_pcie_write(rockchip, desc1, |
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ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); |
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addr0 = |
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((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | |
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(lower_32_bits(cpu_addr) & |
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PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); |
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addr1 = upper_32_bits(cpu_addr); |
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} |
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/* CPU bus address region */ |
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rockchip_pcie_write(rockchip, addr0, |
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ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r)); |
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rockchip_pcie_write(rockchip, addr1, |
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ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r)); |
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} |
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static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, |
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struct pci_epf_header *hdr) |
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{ |
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struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); |
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struct rockchip_pcie *rockchip = &ep->rockchip; |
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/* All functions share the same vendor ID with function 0 */ |
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if (fn == 0) { |
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u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) | |
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(hdr->subsys_vendor_id & GENMASK(31, 16)) << 16; |
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rockchip_pcie_write(rockchip, vid_regs, |
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PCIE_CORE_CONFIG_VENDOR); |
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} |
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rockchip_pcie_write(rockchip, hdr->deviceid << 16, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID); |
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rockchip_pcie_write(rockchip, |
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hdr->revid | |
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hdr->progif_code << 8 | |
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hdr->subclass_code << 16 | |
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hdr->baseclass_code << 24, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_REVISION_ID); |
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rockchip_pcie_write(rockchip, hdr->cache_line_size, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + |
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PCI_CACHE_LINE_SIZE); |
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rockchip_pcie_write(rockchip, hdr->subsys_id << 16, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + |
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PCI_SUBSYSTEM_VENDOR_ID); |
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rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + |
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PCI_INTERRUPT_LINE); |
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return 0; |
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} |
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static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, |
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struct pci_epf_bar *epf_bar) |
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{ |
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struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); |
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struct rockchip_pcie *rockchip = &ep->rockchip; |
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dma_addr_t bar_phys = epf_bar->phys_addr; |
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enum pci_barno bar = epf_bar->barno; |
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int flags = epf_bar->flags; |
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u32 addr0, addr1, reg, cfg, b, aperture, ctrl; |
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u64 sz; |
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/* BAR size is 2^(aperture + 7) */ |
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sz = max_t(size_t, epf_bar->size, MIN_EP_APERTURE); |
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/* |
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* roundup_pow_of_two() returns an unsigned long, which is not suited |
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* for 64bit values. |
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*/ |
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sz = 1ULL << fls64(sz - 1); |
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aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ |
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if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
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ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS; |
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} else { |
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bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH); |
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bool is_64bits = sz > SZ_2G; |
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if (is_64bits && (bar & 1)) |
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return -EINVAL; |
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if (is_64bits && is_prefetch) |
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ctrl = |
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ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; |
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else if (is_prefetch) |
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ctrl = |
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ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS; |
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else if (is_64bits) |
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ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS; |
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else |
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ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS; |
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} |
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if (bar < BAR_4) { |
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reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn); |
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b = bar; |
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} else { |
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reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn); |
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b = bar - BAR_4; |
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} |
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addr0 = lower_32_bits(bar_phys); |
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addr1 = upper_32_bits(bar_phys); |
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cfg = rockchip_pcie_read(rockchip, reg); |
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cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | |
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ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); |
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cfg |= (ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) | |
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ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); |
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rockchip_pcie_write(rockchip, cfg, reg); |
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rockchip_pcie_write(rockchip, addr0, |
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ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar)); |
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rockchip_pcie_write(rockchip, addr1, |
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ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar)); |
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return 0; |
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} |
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static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn, |
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struct pci_epf_bar *epf_bar) |
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{ |
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struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); |
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struct rockchip_pcie *rockchip = &ep->rockchip; |
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u32 reg, cfg, b, ctrl; |
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enum pci_barno bar = epf_bar->barno; |
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if (bar < BAR_4) { |
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reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn); |
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b = bar; |
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} else { |
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reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn); |
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b = bar - BAR_4; |
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} |
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ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED; |
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cfg = rockchip_pcie_read(rockchip, reg); |
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cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | |
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ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); |
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cfg |= ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl); |
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rockchip_pcie_write(rockchip, cfg, reg); |
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rockchip_pcie_write(rockchip, 0x0, |
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ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar)); |
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rockchip_pcie_write(rockchip, 0x0, |
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ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar)); |
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} |
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static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn, |
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phys_addr_t addr, u64 pci_addr, |
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size_t size) |
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{ |
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struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); |
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struct rockchip_pcie *pcie = &ep->rockchip; |
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u32 r; |
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r = find_first_zero_bit(&ep->ob_region_map, |
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sizeof(ep->ob_region_map) * BITS_PER_LONG); |
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/* |
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* Region 0 is reserved for configuration space and shouldn't |
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* be used elsewhere per TRM, so leave it out. |
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*/ |
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if (r >= ep->max_regions - 1) { |
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dev_err(&epc->dev, "no free outbound region\n"); |
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return -EINVAL; |
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} |
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rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, AXI_WRAPPER_MEM_WRITE, addr, |
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pci_addr, size); |
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set_bit(r, &ep->ob_region_map); |
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ep->ob_addr[r] = addr; |
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return 0; |
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} |
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static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn, |
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phys_addr_t addr) |
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{ |
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struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); |
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struct rockchip_pcie *rockchip = &ep->rockchip; |
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u32 r; |
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for (r = 0; r < ep->max_regions - 1; r++) |
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if (ep->ob_addr[r] == addr) |
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break; |
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/* |
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* Region 0 is reserved for configuration space and shouldn't |
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* be used elsewhere per TRM, so leave it out. |
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*/ |
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if (r == ep->max_regions - 1) |
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return; |
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rockchip_pcie_clear_ep_ob_atu(rockchip, r); |
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ep->ob_addr[r] = 0; |
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clear_bit(r, &ep->ob_region_map); |
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} |
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static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, |
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u8 multi_msg_cap) |
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{ |
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struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); |
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struct rockchip_pcie *rockchip = &ep->rockchip; |
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u16 flags; |
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flags = rockchip_pcie_read(rockchip, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + |
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ROCKCHIP_PCIE_EP_MSI_CTRL_REG); |
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flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK; |
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flags |= |
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((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | |
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PCI_MSI_FLAGS_64BIT; |
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flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP; |
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rockchip_pcie_write(rockchip, flags, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + |
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ROCKCHIP_PCIE_EP_MSI_CTRL_REG); |
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return 0; |
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} |
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static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) |
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{ |
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struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); |
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struct rockchip_pcie *rockchip = &ep->rockchip; |
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u16 flags; |
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flags = rockchip_pcie_read(rockchip, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + |
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ROCKCHIP_PCIE_EP_MSI_CTRL_REG); |
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if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME)) |
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return -EINVAL; |
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return ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >> |
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ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET); |
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} |
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static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn, |
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u8 intx, bool is_asserted) |
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{ |
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struct rockchip_pcie *rockchip = &ep->rockchip; |
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u32 r = ep->max_regions - 1; |
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u32 offset; |
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u32 status; |
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u8 msg_code; |
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if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR || |
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ep->irq_pci_fn != fn)) { |
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rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r, |
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AXI_WRAPPER_NOR_MSG, |
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ep->irq_phys_addr, 0, 0); |
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ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR; |
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ep->irq_pci_fn = fn; |
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} |
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intx &= 3; |
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if (is_asserted) { |
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ep->irq_pending |= BIT(intx); |
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msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx; |
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} else { |
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ep->irq_pending &= ~BIT(intx); |
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msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx; |
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} |
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status = rockchip_pcie_read(rockchip, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + |
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ROCKCHIP_PCIE_EP_CMD_STATUS); |
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status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; |
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if ((status != 0) ^ (ep->irq_pending != 0)) { |
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status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; |
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rockchip_pcie_write(rockchip, status, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + |
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ROCKCHIP_PCIE_EP_CMD_STATUS); |
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} |
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offset = |
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ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) | |
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ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA; |
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writel(0, ep->irq_cpu_addr + offset); |
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} |
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static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn, |
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u8 intx) |
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{ |
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u16 cmd; |
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cmd = rockchip_pcie_read(&ep->rockchip, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + |
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ROCKCHIP_PCIE_EP_CMD_STATUS); |
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|
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if (cmd & PCI_COMMAND_INTX_DISABLE) |
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return -EINVAL; |
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|
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/* |
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* Should add some delay between toggling INTx per TRM vaguely saying |
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* it depends on some cycles of the AHB bus clock to function it. So |
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* add sufficient 1ms here. |
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*/ |
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rockchip_pcie_ep_assert_intx(ep, fn, intx, true); |
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mdelay(1); |
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rockchip_pcie_ep_assert_intx(ep, fn, intx, false); |
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return 0; |
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} |
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static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn, |
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u8 interrupt_num) |
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{ |
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struct rockchip_pcie *rockchip = &ep->rockchip; |
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u16 flags, mme, data, data_mask; |
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u8 msi_count; |
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u64 pci_addr, pci_addr_mask = 0xff; |
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|
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/* Check MSI enable bit */ |
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flags = rockchip_pcie_read(&ep->rockchip, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + |
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ROCKCHIP_PCIE_EP_MSI_CTRL_REG); |
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if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME)) |
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return -EINVAL; |
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/* Get MSI numbers from MME */ |
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mme = ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >> |
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ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET); |
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msi_count = 1 << mme; |
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if (!interrupt_num || interrupt_num > msi_count) |
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return -EINVAL; |
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|
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/* Set MSI private data */ |
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data_mask = msi_count - 1; |
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data = rockchip_pcie_read(rockchip, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + |
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ROCKCHIP_PCIE_EP_MSI_CTRL_REG + |
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PCI_MSI_DATA_64); |
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data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask); |
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|
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/* Get MSI PCI address */ |
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pci_addr = rockchip_pcie_read(rockchip, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + |
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ROCKCHIP_PCIE_EP_MSI_CTRL_REG + |
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PCI_MSI_ADDRESS_HI); |
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pci_addr <<= 32; |
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pci_addr |= rockchip_pcie_read(rockchip, |
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + |
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ROCKCHIP_PCIE_EP_MSI_CTRL_REG + |
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PCI_MSI_ADDRESS_LO); |
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pci_addr &= GENMASK_ULL(63, 2); |
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|
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/* Set the outbound region if needed. */ |
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if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) || |
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ep->irq_pci_fn != fn)) { |
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rockchip_pcie_prog_ep_ob_atu(rockchip, fn, ep->max_regions - 1, |
|
AXI_WRAPPER_MEM_WRITE, |
|
ep->irq_phys_addr, |
|
pci_addr & ~pci_addr_mask, |
|
pci_addr_mask + 1); |
|
ep->irq_pci_addr = (pci_addr & ~pci_addr_mask); |
|
ep->irq_pci_fn = fn; |
|
} |
|
|
|
writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); |
|
return 0; |
|
} |
|
|
|
static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn, |
|
enum pci_epc_irq_type type, |
|
u16 interrupt_num) |
|
{ |
|
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); |
|
|
|
switch (type) { |
|
case PCI_EPC_IRQ_LEGACY: |
|
return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0); |
|
case PCI_EPC_IRQ_MSI: |
|
return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num); |
|
default: |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
static int rockchip_pcie_ep_start(struct pci_epc *epc) |
|
{ |
|
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); |
|
struct rockchip_pcie *rockchip = &ep->rockchip; |
|
struct pci_epf *epf; |
|
u32 cfg; |
|
|
|
cfg = BIT(0); |
|
list_for_each_entry(epf, &epc->pci_epf, list) |
|
cfg |= BIT(epf->func_no); |
|
|
|
rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct pci_epc_features rockchip_pcie_epc_features = { |
|
.linkup_notifier = false, |
|
.msi_capable = true, |
|
.msix_capable = false, |
|
}; |
|
|
|
static const struct pci_epc_features* |
|
rockchip_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) |
|
{ |
|
return &rockchip_pcie_epc_features; |
|
} |
|
|
|
static const struct pci_epc_ops rockchip_pcie_epc_ops = { |
|
.write_header = rockchip_pcie_ep_write_header, |
|
.set_bar = rockchip_pcie_ep_set_bar, |
|
.clear_bar = rockchip_pcie_ep_clear_bar, |
|
.map_addr = rockchip_pcie_ep_map_addr, |
|
.unmap_addr = rockchip_pcie_ep_unmap_addr, |
|
.set_msi = rockchip_pcie_ep_set_msi, |
|
.get_msi = rockchip_pcie_ep_get_msi, |
|
.raise_irq = rockchip_pcie_ep_raise_irq, |
|
.start = rockchip_pcie_ep_start, |
|
.get_features = rockchip_pcie_ep_get_features, |
|
}; |
|
|
|
static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip, |
|
struct rockchip_pcie_ep *ep) |
|
{ |
|
struct device *dev = rockchip->dev; |
|
int err; |
|
|
|
err = rockchip_pcie_parse_dt(rockchip); |
|
if (err) |
|
return err; |
|
|
|
err = rockchip_pcie_get_phys(rockchip); |
|
if (err) |
|
return err; |
|
|
|
err = of_property_read_u32(dev->of_node, |
|
"rockchip,max-outbound-regions", |
|
&ep->max_regions); |
|
if (err < 0 || ep->max_regions > MAX_REGION_LIMIT) |
|
ep->max_regions = MAX_REGION_LIMIT; |
|
|
|
err = of_property_read_u8(dev->of_node, "max-functions", |
|
&ep->epc->max_functions); |
|
if (err < 0) |
|
ep->epc->max_functions = 1; |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id rockchip_pcie_ep_of_match[] = { |
|
{ .compatible = "rockchip,rk3399-pcie-ep"}, |
|
{}, |
|
}; |
|
|
|
static int rockchip_pcie_ep_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct rockchip_pcie_ep *ep; |
|
struct rockchip_pcie *rockchip; |
|
struct pci_epc *epc; |
|
size_t max_regions; |
|
int err; |
|
|
|
ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); |
|
if (!ep) |
|
return -ENOMEM; |
|
|
|
rockchip = &ep->rockchip; |
|
rockchip->is_rc = false; |
|
rockchip->dev = dev; |
|
|
|
epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops); |
|
if (IS_ERR(epc)) { |
|
dev_err(dev, "failed to create epc device\n"); |
|
return PTR_ERR(epc); |
|
} |
|
|
|
ep->epc = epc; |
|
epc_set_drvdata(epc, ep); |
|
|
|
err = rockchip_pcie_parse_ep_dt(rockchip, ep); |
|
if (err) |
|
return err; |
|
|
|
err = rockchip_pcie_enable_clocks(rockchip); |
|
if (err) |
|
return err; |
|
|
|
err = rockchip_pcie_init_port(rockchip); |
|
if (err) |
|
goto err_disable_clocks; |
|
|
|
/* Establish the link automatically */ |
|
rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, |
|
PCIE_CLIENT_CONFIG); |
|
|
|
max_regions = ep->max_regions; |
|
ep->ob_addr = devm_kcalloc(dev, max_regions, sizeof(*ep->ob_addr), |
|
GFP_KERNEL); |
|
|
|
if (!ep->ob_addr) { |
|
err = -ENOMEM; |
|
goto err_uninit_port; |
|
} |
|
|
|
/* Only enable function 0 by default */ |
|
rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); |
|
|
|
err = pci_epc_mem_init(epc, rockchip->mem_res->start, |
|
resource_size(rockchip->mem_res), PAGE_SIZE); |
|
if (err < 0) { |
|
dev_err(dev, "failed to initialize the memory space\n"); |
|
goto err_uninit_port; |
|
} |
|
|
|
ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, |
|
SZ_128K); |
|
if (!ep->irq_cpu_addr) { |
|
dev_err(dev, "failed to reserve memory space for MSI\n"); |
|
err = -ENOMEM; |
|
goto err_epc_mem_exit; |
|
} |
|
|
|
ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; |
|
|
|
return 0; |
|
err_epc_mem_exit: |
|
pci_epc_mem_exit(epc); |
|
err_uninit_port: |
|
rockchip_pcie_deinit_phys(rockchip); |
|
err_disable_clocks: |
|
rockchip_pcie_disable_clocks(rockchip); |
|
return err; |
|
} |
|
|
|
static struct platform_driver rockchip_pcie_ep_driver = { |
|
.driver = { |
|
.name = "rockchip-pcie-ep", |
|
.of_match_table = rockchip_pcie_ep_of_match, |
|
}, |
|
.probe = rockchip_pcie_ep_probe, |
|
}; |
|
|
|
builtin_platform_driver(rockchip_pcie_ep_driver);
|
|
|