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593 lines
16 KiB
593 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* PCIe host controller driver for Mobiveil PCIe Host controller |
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* |
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* Copyright (c) 2018 Mobiveil Inc. |
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* Copyright 2019-2020 NXP |
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* |
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* Author: Subrahmanya Lingappa <[email protected]> |
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* Hou Zhiqiang <[email protected]> |
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*/ |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/msi.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_platform.h> |
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#include <linux/of_pci.h> |
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#include <linux/pci.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include "pcie-mobiveil.h" |
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static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) |
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{ |
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/* Only one device down on each root port */ |
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if (pci_is_root_bus(bus) && (devfn > 0)) |
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return false; |
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/* |
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* Do not read more than one device on the bus directly |
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* attached to RC |
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*/ |
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if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) |
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return false; |
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return true; |
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} |
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/* |
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* mobiveil_pcie_map_bus - routine to get the configuration base of either |
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* root port or endpoint |
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*/ |
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static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus, |
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unsigned int devfn, int where) |
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{ |
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struct mobiveil_pcie *pcie = bus->sysdata; |
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struct mobiveil_root_port *rp = &pcie->rp; |
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u32 value; |
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if (!mobiveil_pcie_valid_device(bus, devfn)) |
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return NULL; |
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/* RC config access */ |
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if (pci_is_root_bus(bus)) |
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return pcie->csr_axi_slave_base + where; |
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/* |
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* EP config access (in Config/APIO space) |
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* Program PEX Address base (31..16 bits) with appropriate value |
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* (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register. |
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* Relies on pci_lock serialization |
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*/ |
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value = bus->number << PAB_BUS_SHIFT | |
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PCI_SLOT(devfn) << PAB_DEVICE_SHIFT | |
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PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT; |
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mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); |
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return rp->config_axi_slave_base + where; |
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} |
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static struct pci_ops mobiveil_pcie_ops = { |
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.map_bus = mobiveil_pcie_map_bus, |
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.read = pci_generic_config_read, |
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.write = pci_generic_config_write, |
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}; |
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static void mobiveil_pcie_isr(struct irq_desc *desc) |
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{ |
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struct irq_chip *chip = irq_desc_get_chip(desc); |
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struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); |
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struct device *dev = &pcie->pdev->dev; |
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struct mobiveil_root_port *rp = &pcie->rp; |
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struct mobiveil_msi *msi = &rp->msi; |
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u32 msi_data, msi_addr_lo, msi_addr_hi; |
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u32 intr_status, msi_status; |
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unsigned long shifted_status; |
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u32 bit, val, mask; |
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/* |
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* The core provides a single interrupt for both INTx/MSI messages. |
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* So we'll read both INTx and MSI status |
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*/ |
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chained_irq_enter(chip, desc); |
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/* read INTx status */ |
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val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); |
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mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); |
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intr_status = val & mask; |
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/* Handle INTx */ |
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if (intr_status & PAB_INTP_INTX_MASK) { |
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shifted_status = mobiveil_csr_readl(pcie, |
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PAB_INTP_AMBA_MISC_STAT); |
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shifted_status &= PAB_INTP_INTX_MASK; |
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shifted_status >>= PAB_INTX_START; |
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do { |
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for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) { |
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int ret; |
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ret = generic_handle_domain_irq(rp->intx_domain, |
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bit + 1); |
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if (ret) |
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dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", |
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bit); |
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/* clear interrupt handled */ |
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mobiveil_csr_writel(pcie, |
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1 << (PAB_INTX_START + bit), |
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PAB_INTP_AMBA_MISC_STAT); |
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} |
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shifted_status = mobiveil_csr_readl(pcie, |
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PAB_INTP_AMBA_MISC_STAT); |
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shifted_status &= PAB_INTP_INTX_MASK; |
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shifted_status >>= PAB_INTX_START; |
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} while (shifted_status != 0); |
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} |
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/* read extra MSI status register */ |
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msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET); |
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/* handle MSI interrupts */ |
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while (msi_status & 1) { |
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msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET); |
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/* |
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* MSI_STATUS_OFFSET register gets updated to zero |
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* once we pop not only the MSI data but also address |
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* from MSI hardware FIFO. So keeping these following |
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* two dummy reads. |
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*/ |
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msi_addr_lo = readl_relaxed(pcie->apb_csr_base + |
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MSI_ADDR_L_OFFSET); |
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msi_addr_hi = readl_relaxed(pcie->apb_csr_base + |
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MSI_ADDR_H_OFFSET); |
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dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n", |
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msi_data, msi_addr_hi, msi_addr_lo); |
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generic_handle_domain_irq(msi->dev_domain, msi_data); |
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msi_status = readl_relaxed(pcie->apb_csr_base + |
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MSI_STATUS_OFFSET); |
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} |
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/* Clear the interrupt status */ |
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mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT); |
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chained_irq_exit(chip, desc); |
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} |
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static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) |
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{ |
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struct device *dev = &pcie->pdev->dev; |
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struct platform_device *pdev = pcie->pdev; |
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struct device_node *node = dev->of_node; |
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struct mobiveil_root_port *rp = &pcie->rp; |
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struct resource *res; |
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/* map config resource */ |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
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"config_axi_slave"); |
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rp->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); |
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if (IS_ERR(rp->config_axi_slave_base)) |
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return PTR_ERR(rp->config_axi_slave_base); |
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rp->ob_io_res = res; |
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/* map csr resource */ |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
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"csr_axi_slave"); |
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pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); |
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if (IS_ERR(pcie->csr_axi_slave_base)) |
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return PTR_ERR(pcie->csr_axi_slave_base); |
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pcie->pcie_reg_base = res->start; |
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/* read the number of windows requested */ |
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if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins)) |
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pcie->apio_wins = MAX_PIO_WINDOWS; |
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if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins)) |
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pcie->ppio_wins = MAX_PIO_WINDOWS; |
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return 0; |
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} |
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static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie) |
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{ |
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phys_addr_t msg_addr = pcie->pcie_reg_base; |
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struct mobiveil_msi *msi = &pcie->rp.msi; |
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msi->num_of_vectors = PCI_NUM_MSI; |
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msi->msi_pages_phys = (phys_addr_t)msg_addr; |
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writel_relaxed(lower_32_bits(msg_addr), |
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pcie->apb_csr_base + MSI_BASE_LO_OFFSET); |
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writel_relaxed(upper_32_bits(msg_addr), |
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pcie->apb_csr_base + MSI_BASE_HI_OFFSET); |
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writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET); |
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writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); |
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} |
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int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit) |
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{ |
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struct mobiveil_root_port *rp = &pcie->rp; |
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struct pci_host_bridge *bridge = rp->bridge; |
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u32 value, pab_ctrl, type; |
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struct resource_entry *win; |
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pcie->ib_wins_configured = 0; |
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pcie->ob_wins_configured = 0; |
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if (!reinit) { |
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/* setup bus numbers */ |
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value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS); |
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value &= 0xff000000; |
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value |= 0x00ff0100; |
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mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS); |
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} |
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/* |
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* program Bus Master Enable Bit in Command Register in PAB Config |
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* Space |
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*/ |
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value = mobiveil_csr_readl(pcie, PCI_COMMAND); |
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value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; |
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mobiveil_csr_writel(pcie, value, PCI_COMMAND); |
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/* |
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* program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL |
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* register |
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*/ |
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pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL); |
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pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT); |
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mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL); |
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/* |
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* program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in |
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* PAB_AXI_PIO_CTRL Register |
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*/ |
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value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL); |
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value |= APIO_EN_MASK; |
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mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL); |
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/* Enable PCIe PIO master */ |
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value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL); |
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value |= 1 << PIO_ENABLE_SHIFT; |
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mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL); |
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/* |
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* we'll program one outbound window for config reads and |
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* another default inbound window for all the upstream traffic |
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* rest of the outbound windows will be configured according to |
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* the "ranges" field defined in device tree |
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*/ |
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/* config outbound translation window */ |
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program_ob_windows(pcie, WIN_NUM_0, rp->ob_io_res->start, 0, |
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CFG_WINDOW_TYPE, resource_size(rp->ob_io_res)); |
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/* memory inbound translation window */ |
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program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); |
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/* Get the I/O and memory ranges from DT */ |
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resource_list_for_each_entry(win, &bridge->windows) { |
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if (resource_type(win->res) == IORESOURCE_MEM) |
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type = MEM_WINDOW_TYPE; |
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else if (resource_type(win->res) == IORESOURCE_IO) |
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type = IO_WINDOW_TYPE; |
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else |
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continue; |
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/* configure outbound translation window */ |
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program_ob_windows(pcie, pcie->ob_wins_configured, |
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win->res->start, |
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win->res->start - win->offset, |
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type, resource_size(win->res)); |
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} |
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/* fixup for PCIe class register */ |
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value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS); |
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value &= 0xff; |
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value |= (PCI_CLASS_BRIDGE_PCI << 16); |
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mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); |
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return 0; |
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} |
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static void mobiveil_mask_intx_irq(struct irq_data *data) |
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{ |
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struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data); |
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struct mobiveil_root_port *rp; |
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unsigned long flags; |
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u32 mask, shifted_val; |
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rp = &pcie->rp; |
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mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); |
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raw_spin_lock_irqsave(&rp->intx_mask_lock, flags); |
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shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); |
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shifted_val &= ~mask; |
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mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB); |
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raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags); |
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} |
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static void mobiveil_unmask_intx_irq(struct irq_data *data) |
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{ |
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struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data); |
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struct mobiveil_root_port *rp; |
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unsigned long flags; |
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u32 shifted_val, mask; |
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rp = &pcie->rp; |
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mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); |
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raw_spin_lock_irqsave(&rp->intx_mask_lock, flags); |
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shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); |
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shifted_val |= mask; |
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mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB); |
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raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags); |
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} |
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static struct irq_chip intx_irq_chip = { |
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.name = "mobiveil_pcie:intx", |
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.irq_enable = mobiveil_unmask_intx_irq, |
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.irq_disable = mobiveil_mask_intx_irq, |
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.irq_mask = mobiveil_mask_intx_irq, |
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.irq_unmask = mobiveil_unmask_intx_irq, |
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}; |
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/* routine to setup the INTx related data */ |
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static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq, |
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irq_hw_number_t hwirq) |
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{ |
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irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq); |
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irq_set_chip_data(irq, domain->host_data); |
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return 0; |
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} |
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/* INTx domain operations structure */ |
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static const struct irq_domain_ops intx_domain_ops = { |
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.map = mobiveil_pcie_intx_map, |
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}; |
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static struct irq_chip mobiveil_msi_irq_chip = { |
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.name = "Mobiveil PCIe MSI", |
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.irq_mask = pci_msi_mask_irq, |
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.irq_unmask = pci_msi_unmask_irq, |
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}; |
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static struct msi_domain_info mobiveil_msi_domain_info = { |
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | |
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MSI_FLAG_PCI_MSIX), |
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.chip = &mobiveil_msi_irq_chip, |
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}; |
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static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) |
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{ |
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struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data); |
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phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int)); |
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msg->address_lo = lower_32_bits(addr); |
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msg->address_hi = upper_32_bits(addr); |
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msg->data = data->hwirq; |
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dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n", |
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(int)data->hwirq, msg->address_hi, msg->address_lo); |
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} |
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static int mobiveil_msi_set_affinity(struct irq_data *irq_data, |
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const struct cpumask *mask, bool force) |
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{ |
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return -EINVAL; |
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} |
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static struct irq_chip mobiveil_msi_bottom_irq_chip = { |
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.name = "Mobiveil MSI", |
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.irq_compose_msi_msg = mobiveil_compose_msi_msg, |
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.irq_set_affinity = mobiveil_msi_set_affinity, |
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}; |
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static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain, |
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unsigned int virq, |
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unsigned int nr_irqs, void *args) |
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{ |
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struct mobiveil_pcie *pcie = domain->host_data; |
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struct mobiveil_msi *msi = &pcie->rp.msi; |
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unsigned long bit; |
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WARN_ON(nr_irqs != 1); |
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mutex_lock(&msi->lock); |
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bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors); |
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if (bit >= msi->num_of_vectors) { |
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mutex_unlock(&msi->lock); |
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return -ENOSPC; |
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} |
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set_bit(bit, msi->msi_irq_in_use); |
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mutex_unlock(&msi->lock); |
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irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip, |
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domain->host_data, handle_level_irq, NULL, NULL); |
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return 0; |
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} |
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static void mobiveil_irq_msi_domain_free(struct irq_domain *domain, |
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unsigned int virq, |
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unsigned int nr_irqs) |
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{ |
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struct irq_data *d = irq_domain_get_irq_data(domain, virq); |
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struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d); |
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struct mobiveil_msi *msi = &pcie->rp.msi; |
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mutex_lock(&msi->lock); |
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if (!test_bit(d->hwirq, msi->msi_irq_in_use)) |
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dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n", |
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d->hwirq); |
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else |
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__clear_bit(d->hwirq, msi->msi_irq_in_use); |
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mutex_unlock(&msi->lock); |
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} |
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static const struct irq_domain_ops msi_domain_ops = { |
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.alloc = mobiveil_irq_msi_domain_alloc, |
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.free = mobiveil_irq_msi_domain_free, |
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}; |
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static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie) |
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{ |
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struct device *dev = &pcie->pdev->dev; |
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struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); |
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struct mobiveil_msi *msi = &pcie->rp.msi; |
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mutex_init(&msi->lock); |
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msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors, |
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&msi_domain_ops, pcie); |
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if (!msi->dev_domain) { |
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dev_err(dev, "failed to create IRQ domain\n"); |
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return -ENOMEM; |
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} |
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msi->msi_domain = pci_msi_create_irq_domain(fwnode, |
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&mobiveil_msi_domain_info, |
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msi->dev_domain); |
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if (!msi->msi_domain) { |
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dev_err(dev, "failed to create MSI domain\n"); |
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irq_domain_remove(msi->dev_domain); |
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return -ENOMEM; |
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} |
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return 0; |
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} |
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static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) |
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{ |
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struct device *dev = &pcie->pdev->dev; |
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struct device_node *node = dev->of_node; |
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struct mobiveil_root_port *rp = &pcie->rp; |
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/* setup INTx */ |
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rp->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX, |
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&intx_domain_ops, pcie); |
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if (!rp->intx_domain) { |
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dev_err(dev, "Failed to get a INTx IRQ domain\n"); |
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return -ENOMEM; |
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} |
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raw_spin_lock_init(&rp->intx_mask_lock); |
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/* setup MSI */ |
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return mobiveil_allocate_msi_domains(pcie); |
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} |
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static int mobiveil_pcie_integrated_interrupt_init(struct mobiveil_pcie *pcie) |
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{ |
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struct platform_device *pdev = pcie->pdev; |
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struct device *dev = &pdev->dev; |
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struct mobiveil_root_port *rp = &pcie->rp; |
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struct resource *res; |
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int ret; |
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|
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/* map MSI config resource */ |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr"); |
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pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); |
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if (IS_ERR(pcie->apb_csr_base)) |
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return PTR_ERR(pcie->apb_csr_base); |
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|
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/* setup MSI hardware registers */ |
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mobiveil_pcie_enable_msi(pcie); |
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|
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rp->irq = platform_get_irq(pdev, 0); |
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if (rp->irq < 0) |
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return rp->irq; |
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|
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/* initialize the IRQ domains */ |
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ret = mobiveil_pcie_init_irq_domain(pcie); |
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if (ret) { |
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dev_err(dev, "Failed creating IRQ Domain\n"); |
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return ret; |
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} |
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|
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irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); |
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|
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/* Enable interrupts */ |
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mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), |
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PAB_INTP_AMBA_MISC_ENB); |
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|
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return 0; |
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} |
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|
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static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie) |
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{ |
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struct mobiveil_root_port *rp = &pcie->rp; |
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|
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if (rp->ops->interrupt_init) |
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return rp->ops->interrupt_init(pcie); |
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|
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return mobiveil_pcie_integrated_interrupt_init(pcie); |
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} |
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|
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static bool mobiveil_pcie_is_bridge(struct mobiveil_pcie *pcie) |
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{ |
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u32 header_type; |
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|
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header_type = mobiveil_csr_readb(pcie, PCI_HEADER_TYPE); |
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header_type &= 0x7f; |
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|
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return header_type == PCI_HEADER_TYPE_BRIDGE; |
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} |
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|
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int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) |
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{ |
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struct mobiveil_root_port *rp = &pcie->rp; |
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struct pci_host_bridge *bridge = rp->bridge; |
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struct device *dev = &pcie->pdev->dev; |
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int ret; |
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|
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ret = mobiveil_pcie_parse_dt(pcie); |
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if (ret) { |
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dev_err(dev, "Parsing DT failed, ret: %x\n", ret); |
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return ret; |
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} |
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|
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if (!mobiveil_pcie_is_bridge(pcie)) |
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return -ENODEV; |
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|
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/* |
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* configure all inbound and outbound windows and prepare the RC for |
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* config access |
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*/ |
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ret = mobiveil_host_init(pcie, false); |
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if (ret) { |
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dev_err(dev, "Failed to initialize host\n"); |
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return ret; |
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} |
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|
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ret = mobiveil_pcie_interrupt_init(pcie); |
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if (ret) { |
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dev_err(dev, "Interrupt init failed\n"); |
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return ret; |
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} |
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|
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/* Initialize bridge */ |
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bridge->sysdata = pcie; |
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bridge->ops = &mobiveil_pcie_ops; |
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|
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ret = mobiveil_bringup_link(pcie); |
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if (ret) { |
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dev_info(dev, "link bring-up failed\n"); |
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return ret; |
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} |
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|
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return pci_host_probe(bridge); |
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}
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