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486 lines
12 KiB
486 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* PCIe host controller driver for Kirin Phone SoCs |
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* |
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* Copyright (C) 2017 HiSilicon Electronics Co., Ltd. |
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* https://www.huawei.com |
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* |
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* Author: Xiaowei Song <[email protected]> |
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*/ |
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#include <linux/compiler.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/gpio.h> |
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#include <linux/interrupt.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/of_address.h> |
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#include <linux/of_gpio.h> |
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#include <linux/of_pci.h> |
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#include <linux/pci.h> |
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#include <linux/pci_regs.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/resource.h> |
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#include <linux/types.h> |
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#include "pcie-designware.h" |
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#define to_kirin_pcie(x) dev_get_drvdata((x)->dev) |
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#define REF_CLK_FREQ 100000000 |
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/* PCIe ELBI registers */ |
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#define SOC_PCIECTRL_CTRL0_ADDR 0x000 |
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#define SOC_PCIECTRL_CTRL1_ADDR 0x004 |
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#define SOC_PCIEPHY_CTRL2_ADDR 0x008 |
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#define SOC_PCIEPHY_CTRL3_ADDR 0x00c |
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#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) |
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/* info located in APB */ |
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#define PCIE_APP_LTSSM_ENABLE 0x01c |
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#define PCIE_APB_PHY_CTRL0 0x0 |
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#define PCIE_APB_PHY_CTRL1 0x4 |
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#define PCIE_APB_PHY_STATUS0 0x400 |
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#define PCIE_LINKUP_ENABLE (0x8020) |
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#define PCIE_LTSSM_ENABLE_BIT (0x1 << 11) |
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#define PIPE_CLK_STABLE (0x1 << 19) |
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#define PHY_REF_PAD_BIT (0x1 << 8) |
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#define PHY_PWR_DOWN_BIT (0x1 << 22) |
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#define PHY_RST_ACK_BIT (0x1 << 16) |
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/* info located in sysctrl */ |
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#define SCTRL_PCIE_CMOS_OFFSET 0x60 |
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#define SCTRL_PCIE_CMOS_BIT 0x10 |
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#define SCTRL_PCIE_ISO_OFFSET 0x44 |
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#define SCTRL_PCIE_ISO_BIT 0x30 |
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#define SCTRL_PCIE_HPCLK_OFFSET 0x190 |
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#define SCTRL_PCIE_HPCLK_BIT 0x184000 |
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#define SCTRL_PCIE_OE_OFFSET 0x14a |
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#define PCIE_DEBOUNCE_PARAM 0xF0F400 |
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#define PCIE_OE_BYPASS (0x3 << 28) |
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/* peri_crg ctrl */ |
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#define CRGCTRL_PCIE_ASSERT_OFFSET 0x88 |
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#define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000 |
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/* Time for delay */ |
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#define REF_2_PERST_MIN 20000 |
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#define REF_2_PERST_MAX 25000 |
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#define PERST_2_ACCESS_MIN 10000 |
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#define PERST_2_ACCESS_MAX 12000 |
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#define LINK_WAIT_MIN 900 |
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#define LINK_WAIT_MAX 1000 |
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#define PIPE_CLK_WAIT_MIN 550 |
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#define PIPE_CLK_WAIT_MAX 600 |
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#define TIME_CMOS_MIN 100 |
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#define TIME_CMOS_MAX 105 |
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#define TIME_PHY_PD_MIN 10 |
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#define TIME_PHY_PD_MAX 11 |
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struct kirin_pcie { |
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struct dw_pcie *pci; |
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void __iomem *apb_base; |
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void __iomem *phy_base; |
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struct regmap *crgctrl; |
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struct regmap *sysctrl; |
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struct clk *apb_sys_clk; |
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struct clk *apb_phy_clk; |
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struct clk *phy_ref_clk; |
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struct clk *pcie_aclk; |
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struct clk *pcie_aux_clk; |
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int gpio_id_reset; |
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}; |
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/* Registers in PCIeCTRL */ |
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static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie, |
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u32 val, u32 reg) |
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{ |
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writel(val, kirin_pcie->apb_base + reg); |
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} |
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static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg) |
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{ |
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return readl(kirin_pcie->apb_base + reg); |
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} |
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/* Registers in PCIePHY */ |
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static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie, |
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u32 val, u32 reg) |
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{ |
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writel(val, kirin_pcie->phy_base + reg); |
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} |
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static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg) |
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{ |
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return readl(kirin_pcie->phy_base + reg); |
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} |
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static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie, |
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struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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kirin_pcie->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref"); |
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if (IS_ERR(kirin_pcie->phy_ref_clk)) |
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return PTR_ERR(kirin_pcie->phy_ref_clk); |
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kirin_pcie->pcie_aux_clk = devm_clk_get(dev, "pcie_aux"); |
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if (IS_ERR(kirin_pcie->pcie_aux_clk)) |
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return PTR_ERR(kirin_pcie->pcie_aux_clk); |
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kirin_pcie->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy"); |
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if (IS_ERR(kirin_pcie->apb_phy_clk)) |
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return PTR_ERR(kirin_pcie->apb_phy_clk); |
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kirin_pcie->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys"); |
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if (IS_ERR(kirin_pcie->apb_sys_clk)) |
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return PTR_ERR(kirin_pcie->apb_sys_clk); |
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kirin_pcie->pcie_aclk = devm_clk_get(dev, "pcie_aclk"); |
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if (IS_ERR(kirin_pcie->pcie_aclk)) |
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return PTR_ERR(kirin_pcie->pcie_aclk); |
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return 0; |
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} |
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static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, |
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struct platform_device *pdev) |
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{ |
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kirin_pcie->apb_base = |
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devm_platform_ioremap_resource_byname(pdev, "apb"); |
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if (IS_ERR(kirin_pcie->apb_base)) |
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return PTR_ERR(kirin_pcie->apb_base); |
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kirin_pcie->phy_base = |
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devm_platform_ioremap_resource_byname(pdev, "phy"); |
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if (IS_ERR(kirin_pcie->phy_base)) |
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return PTR_ERR(kirin_pcie->phy_base); |
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kirin_pcie->crgctrl = |
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syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl"); |
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if (IS_ERR(kirin_pcie->crgctrl)) |
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return PTR_ERR(kirin_pcie->crgctrl); |
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kirin_pcie->sysctrl = |
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syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl"); |
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if (IS_ERR(kirin_pcie->sysctrl)) |
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return PTR_ERR(kirin_pcie->sysctrl); |
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return 0; |
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} |
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static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie) |
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{ |
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struct device *dev = kirin_pcie->pci->dev; |
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u32 reg_val; |
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reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1); |
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reg_val &= ~PHY_REF_PAD_BIT; |
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kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1); |
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reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0); |
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reg_val &= ~PHY_PWR_DOWN_BIT; |
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kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0); |
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usleep_range(TIME_PHY_PD_MIN, TIME_PHY_PD_MAX); |
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reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1); |
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reg_val &= ~PHY_RST_ACK_BIT; |
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kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1); |
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usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX); |
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reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0); |
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if (reg_val & PIPE_CLK_STABLE) { |
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dev_err(dev, "PIPE clk is not stable\n"); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie) |
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{ |
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u32 val; |
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regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val); |
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val |= PCIE_DEBOUNCE_PARAM; |
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val &= ~PCIE_OE_BYPASS; |
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regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val); |
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} |
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static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable) |
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{ |
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int ret = 0; |
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if (!enable) |
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goto close_clk; |
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ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(kirin_pcie->phy_ref_clk); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(kirin_pcie->apb_sys_clk); |
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if (ret) |
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goto apb_sys_fail; |
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ret = clk_prepare_enable(kirin_pcie->apb_phy_clk); |
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if (ret) |
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goto apb_phy_fail; |
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ret = clk_prepare_enable(kirin_pcie->pcie_aclk); |
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if (ret) |
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goto aclk_fail; |
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ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk); |
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if (ret) |
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goto aux_clk_fail; |
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return 0; |
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close_clk: |
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clk_disable_unprepare(kirin_pcie->pcie_aux_clk); |
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aux_clk_fail: |
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clk_disable_unprepare(kirin_pcie->pcie_aclk); |
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aclk_fail: |
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clk_disable_unprepare(kirin_pcie->apb_phy_clk); |
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apb_phy_fail: |
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clk_disable_unprepare(kirin_pcie->apb_sys_clk); |
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apb_sys_fail: |
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clk_disable_unprepare(kirin_pcie->phy_ref_clk); |
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return ret; |
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} |
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static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie) |
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{ |
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int ret; |
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/* Power supply for Host */ |
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regmap_write(kirin_pcie->sysctrl, |
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SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT); |
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usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX); |
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kirin_pcie_oe_enable(kirin_pcie); |
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ret = kirin_pcie_clk_ctrl(kirin_pcie, true); |
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if (ret) |
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return ret; |
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/* ISO disable, PCIeCtrl, PHY assert and clk gate clear */ |
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regmap_write(kirin_pcie->sysctrl, |
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SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT); |
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regmap_write(kirin_pcie->crgctrl, |
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CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT); |
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regmap_write(kirin_pcie->sysctrl, |
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SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT); |
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ret = kirin_pcie_phy_init(kirin_pcie); |
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if (ret) |
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goto close_clk; |
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/* perst assert Endpoint */ |
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if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) { |
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usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX); |
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ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1); |
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if (ret) |
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goto close_clk; |
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usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); |
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return 0; |
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} |
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close_clk: |
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kirin_pcie_clk_ctrl(kirin_pcie, false); |
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return ret; |
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} |
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static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie, |
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bool on) |
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{ |
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u32 val; |
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val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR); |
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if (on) |
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val = val | PCIE_ELBI_SLV_DBI_ENABLE; |
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else |
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val = val & ~PCIE_ELBI_SLV_DBI_ENABLE; |
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kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR); |
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} |
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static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie, |
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bool on) |
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{ |
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u32 val; |
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val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR); |
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if (on) |
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val = val | PCIE_ELBI_SLV_DBI_ENABLE; |
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else |
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val = val & ~PCIE_ELBI_SLV_DBI_ENABLE; |
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kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR); |
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} |
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static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *val) |
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{ |
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struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); |
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if (PCI_SLOT(devfn)) { |
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*val = ~0; |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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} |
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*val = dw_pcie_read_dbi(pci, where, size); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int kirin_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 val) |
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{ |
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struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); |
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if (PCI_SLOT(devfn)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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dw_pcie_write_dbi(pci, where, size, val); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static struct pci_ops kirin_pci_ops = { |
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.read = kirin_pcie_rd_own_conf, |
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.write = kirin_pcie_wr_own_conf, |
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}; |
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static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, |
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u32 reg, size_t size) |
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{ |
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struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); |
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u32 ret; |
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kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true); |
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dw_pcie_read(base + reg, size, &ret); |
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kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false); |
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return ret; |
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} |
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static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, |
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u32 reg, size_t size, u32 val) |
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{ |
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struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); |
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kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true); |
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dw_pcie_write(base + reg, size, val); |
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kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false); |
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} |
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static int kirin_pcie_link_up(struct dw_pcie *pci) |
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{ |
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struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); |
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u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0); |
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if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE) |
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return 1; |
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return 0; |
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} |
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static int kirin_pcie_start_link(struct dw_pcie *pci) |
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{ |
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struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); |
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/* assert LTSSM enable */ |
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kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT, |
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PCIE_APP_LTSSM_ENABLE); |
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return 0; |
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} |
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static int kirin_pcie_host_init(struct pcie_port *pp) |
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{ |
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pp->bridge->ops = &kirin_pci_ops; |
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return 0; |
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} |
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static const struct dw_pcie_ops kirin_dw_pcie_ops = { |
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.read_dbi = kirin_pcie_read_dbi, |
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.write_dbi = kirin_pcie_write_dbi, |
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.link_up = kirin_pcie_link_up, |
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.start_link = kirin_pcie_start_link, |
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}; |
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static const struct dw_pcie_host_ops kirin_pcie_host_ops = { |
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.host_init = kirin_pcie_host_init, |
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}; |
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static int kirin_pcie_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct kirin_pcie *kirin_pcie; |
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struct dw_pcie *pci; |
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int ret; |
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if (!dev->of_node) { |
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dev_err(dev, "NULL node\n"); |
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return -EINVAL; |
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} |
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kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL); |
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if (!kirin_pcie) |
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return -ENOMEM; |
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pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); |
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if (!pci) |
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return -ENOMEM; |
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pci->dev = dev; |
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pci->ops = &kirin_dw_pcie_ops; |
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pci->pp.ops = &kirin_pcie_host_ops; |
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kirin_pcie->pci = pci; |
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ret = kirin_pcie_get_clk(kirin_pcie, pdev); |
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if (ret) |
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return ret; |
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ret = kirin_pcie_get_resource(kirin_pcie, pdev); |
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if (ret) |
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return ret; |
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kirin_pcie->gpio_id_reset = of_get_named_gpio(dev->of_node, |
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"reset-gpios", 0); |
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if (kirin_pcie->gpio_id_reset == -EPROBE_DEFER) { |
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return -EPROBE_DEFER; |
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} else if (!gpio_is_valid(kirin_pcie->gpio_id_reset)) { |
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dev_err(dev, "unable to get a valid gpio pin\n"); |
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return -ENODEV; |
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} |
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ret = kirin_pcie_power_on(kirin_pcie); |
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if (ret) |
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return ret; |
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platform_set_drvdata(pdev, kirin_pcie); |
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return dw_pcie_host_init(&pci->pp); |
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} |
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static const struct of_device_id kirin_pcie_match[] = { |
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{ .compatible = "hisilicon,kirin960-pcie" }, |
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{}, |
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}; |
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static struct platform_driver kirin_pcie_driver = { |
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.probe = kirin_pcie_probe, |
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.driver = { |
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.name = "kirin-pcie", |
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.of_match_table = kirin_pcie_match, |
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.suppress_bind_attrs = true, |
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}, |
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}; |
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builtin_platform_driver(kirin_pcie_driver);
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