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460 lines
11 KiB
460 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* PCIe controller driver for Intel Keem Bay |
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* Copyright (C) 2020 Intel Corporation |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/bits.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/gpio/consumer.h> |
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#include <linux/init.h> |
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#include <linux/iopoll.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/kernel.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/pci.h> |
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#include <linux/platform_device.h> |
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#include <linux/property.h> |
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#include "pcie-designware.h" |
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/* PCIE_REGS_APB_SLV Registers */ |
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#define PCIE_REGS_PCIE_CFG 0x0004 |
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#define PCIE_DEVICE_TYPE BIT(8) |
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#define PCIE_RSTN BIT(0) |
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#define PCIE_REGS_PCIE_APP_CNTRL 0x0008 |
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#define APP_LTSSM_ENABLE BIT(0) |
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#define PCIE_REGS_INTERRUPT_ENABLE 0x0028 |
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#define MSI_CTRL_INT_EN BIT(8) |
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#define EDMA_INT_EN GENMASK(7, 0) |
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#define PCIE_REGS_INTERRUPT_STATUS 0x002c |
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#define MSI_CTRL_INT BIT(8) |
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#define PCIE_REGS_PCIE_SII_PM_STATE 0x00b0 |
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#define SMLH_LINK_UP BIT(19) |
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#define RDLH_LINK_UP BIT(8) |
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#define PCIE_REGS_PCIE_SII_LINK_UP (SMLH_LINK_UP | RDLH_LINK_UP) |
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#define PCIE_REGS_PCIE_PHY_CNTL 0x0164 |
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#define PHY0_SRAM_BYPASS BIT(8) |
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#define PCIE_REGS_PCIE_PHY_STAT 0x0168 |
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#define PHY0_MPLLA_STATE BIT(1) |
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#define PCIE_REGS_LJPLL_STA 0x016c |
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#define LJPLL_LOCK BIT(0) |
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#define PCIE_REGS_LJPLL_CNTRL_0 0x0170 |
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#define LJPLL_EN BIT(29) |
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#define LJPLL_FOUT_EN GENMASK(24, 21) |
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#define PCIE_REGS_LJPLL_CNTRL_2 0x0178 |
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#define LJPLL_REF_DIV GENMASK(17, 12) |
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#define LJPLL_FB_DIV GENMASK(11, 0) |
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#define PCIE_REGS_LJPLL_CNTRL_3 0x017c |
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#define LJPLL_POST_DIV3A GENMASK(24, 22) |
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#define LJPLL_POST_DIV2A GENMASK(18, 16) |
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#define PERST_DELAY_US 1000 |
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#define AUX_CLK_RATE_HZ 24000000 |
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struct keembay_pcie { |
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struct dw_pcie pci; |
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void __iomem *apb_base; |
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enum dw_pcie_device_mode mode; |
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struct clk *clk_master; |
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struct clk *clk_aux; |
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struct gpio_desc *reset; |
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}; |
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struct keembay_pcie_of_data { |
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enum dw_pcie_device_mode mode; |
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}; |
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static void keembay_ep_reset_assert(struct keembay_pcie *pcie) |
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{ |
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gpiod_set_value_cansleep(pcie->reset, 1); |
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usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); |
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} |
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static void keembay_ep_reset_deassert(struct keembay_pcie *pcie) |
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{ |
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/* |
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* Ensure that PERST# is asserted for a minimum of 100ms. |
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* |
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* For more details, refer to PCI Express Card Electromechanical |
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* Specification Revision 1.1, Table-2.4. |
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*/ |
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msleep(100); |
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gpiod_set_value_cansleep(pcie->reset, 0); |
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usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); |
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} |
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static void keembay_pcie_ltssm_set(struct keembay_pcie *pcie, bool enable) |
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{ |
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u32 val; |
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val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); |
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if (enable) |
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val |= APP_LTSSM_ENABLE; |
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else |
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val &= ~APP_LTSSM_ENABLE; |
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writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); |
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} |
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static int keembay_pcie_link_up(struct dw_pcie *pci) |
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{ |
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struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); |
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u32 val; |
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val = readl(pcie->apb_base + PCIE_REGS_PCIE_SII_PM_STATE); |
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return (val & PCIE_REGS_PCIE_SII_LINK_UP) == PCIE_REGS_PCIE_SII_LINK_UP; |
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} |
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static int keembay_pcie_start_link(struct dw_pcie *pci) |
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{ |
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struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); |
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u32 val; |
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int ret; |
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if (pcie->mode == DW_PCIE_EP_TYPE) |
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return 0; |
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keembay_pcie_ltssm_set(pcie, false); |
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ret = readl_poll_timeout(pcie->apb_base + PCIE_REGS_PCIE_PHY_STAT, |
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val, val & PHY0_MPLLA_STATE, 20, |
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500 * USEC_PER_MSEC); |
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if (ret) { |
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dev_err(pci->dev, "MPLLA is not locked\n"); |
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return ret; |
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} |
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keembay_pcie_ltssm_set(pcie, true); |
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return 0; |
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} |
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static void keembay_pcie_stop_link(struct dw_pcie *pci) |
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{ |
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struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); |
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keembay_pcie_ltssm_set(pcie, false); |
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} |
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static const struct dw_pcie_ops keembay_pcie_ops = { |
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.link_up = keembay_pcie_link_up, |
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.start_link = keembay_pcie_start_link, |
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.stop_link = keembay_pcie_stop_link, |
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}; |
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static inline struct clk *keembay_pcie_probe_clock(struct device *dev, |
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const char *id, u64 rate) |
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{ |
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struct clk *clk; |
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int ret; |
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clk = devm_clk_get(dev, id); |
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if (IS_ERR(clk)) |
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return clk; |
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if (rate) { |
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ret = clk_set_rate(clk, rate); |
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if (ret) |
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return ERR_PTR(ret); |
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} |
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ret = clk_prepare_enable(clk); |
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if (ret) |
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return ERR_PTR(ret); |
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ret = devm_add_action_or_reset(dev, |
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(void(*)(void *))clk_disable_unprepare, |
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clk); |
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if (ret) |
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return ERR_PTR(ret); |
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return clk; |
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} |
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static int keembay_pcie_probe_clocks(struct keembay_pcie *pcie) |
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{ |
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struct dw_pcie *pci = &pcie->pci; |
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struct device *dev = pci->dev; |
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pcie->clk_master = keembay_pcie_probe_clock(dev, "master", 0); |
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if (IS_ERR(pcie->clk_master)) |
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return dev_err_probe(dev, PTR_ERR(pcie->clk_master), |
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"Failed to enable master clock"); |
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pcie->clk_aux = keembay_pcie_probe_clock(dev, "aux", AUX_CLK_RATE_HZ); |
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if (IS_ERR(pcie->clk_aux)) |
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return dev_err_probe(dev, PTR_ERR(pcie->clk_aux), |
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"Failed to enable auxiliary clock"); |
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return 0; |
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} |
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/* |
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* Initialize the internal PCIe PLL in Host mode. |
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* See the following sections in Keem Bay data book, |
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* (1) 6.4.6.1 PCIe Subsystem Example Initialization, |
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* (2) 6.8 PCIe Low Jitter PLL for Ref Clk Generation. |
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*/ |
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static int keembay_pcie_pll_init(struct keembay_pcie *pcie) |
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{ |
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struct dw_pcie *pci = &pcie->pci; |
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u32 val; |
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int ret; |
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val = FIELD_PREP(LJPLL_REF_DIV, 0) | FIELD_PREP(LJPLL_FB_DIV, 0x32); |
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writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_2); |
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val = FIELD_PREP(LJPLL_POST_DIV3A, 0x2) | |
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FIELD_PREP(LJPLL_POST_DIV2A, 0x2); |
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writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_3); |
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val = FIELD_PREP(LJPLL_EN, 0x1) | FIELD_PREP(LJPLL_FOUT_EN, 0xc); |
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writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_0); |
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ret = readl_poll_timeout(pcie->apb_base + PCIE_REGS_LJPLL_STA, |
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val, val & LJPLL_LOCK, 20, |
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500 * USEC_PER_MSEC); |
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if (ret) |
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dev_err(pci->dev, "Low jitter PLL is not locked\n"); |
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return ret; |
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} |
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static void keembay_pcie_msi_irq_handler(struct irq_desc *desc) |
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{ |
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struct keembay_pcie *pcie = irq_desc_get_handler_data(desc); |
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struct irq_chip *chip = irq_desc_get_chip(desc); |
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u32 val, mask, status; |
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struct pcie_port *pp; |
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/* |
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* Keem Bay PCIe Controller provides an additional IP logic on top of |
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* standard DWC IP to clear MSI IRQ by writing '1' to the respective |
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* bit of the status register. |
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* |
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* So, a chained irq handler is defined to handle this additional |
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* IP logic. |
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*/ |
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chained_irq_enter(chip, desc); |
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pp = &pcie->pci.pp; |
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val = readl(pcie->apb_base + PCIE_REGS_INTERRUPT_STATUS); |
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mask = readl(pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE); |
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status = val & mask; |
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if (status & MSI_CTRL_INT) { |
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dw_handle_msi_irq(pp); |
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writel(status, pcie->apb_base + PCIE_REGS_INTERRUPT_STATUS); |
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} |
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chained_irq_exit(chip, desc); |
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} |
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static int keembay_pcie_setup_msi_irq(struct keembay_pcie *pcie) |
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{ |
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struct dw_pcie *pci = &pcie->pci; |
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struct device *dev = pci->dev; |
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struct platform_device *pdev = to_platform_device(dev); |
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int irq; |
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irq = platform_get_irq_byname(pdev, "pcie"); |
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if (irq < 0) |
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return irq; |
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irq_set_chained_handler_and_data(irq, keembay_pcie_msi_irq_handler, |
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pcie); |
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return 0; |
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} |
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static void keembay_pcie_ep_init(struct dw_pcie_ep *ep) |
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{ |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); |
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writel(EDMA_INT_EN, pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE); |
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} |
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static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, |
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enum pci_epc_irq_type type, |
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u16 interrupt_num) |
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{ |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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switch (type) { |
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case PCI_EPC_IRQ_LEGACY: |
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/* Legacy interrupts are not supported in Keem Bay */ |
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dev_err(pci->dev, "Legacy IRQ is not supported\n"); |
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return -EINVAL; |
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case PCI_EPC_IRQ_MSI: |
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return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); |
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case PCI_EPC_IRQ_MSIX: |
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return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); |
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default: |
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dev_err(pci->dev, "Unknown IRQ type %d\n", type); |
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return -EINVAL; |
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} |
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} |
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static const struct pci_epc_features keembay_pcie_epc_features = { |
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.linkup_notifier = false, |
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.msi_capable = true, |
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.msix_capable = true, |
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.reserved_bar = BIT(BAR_1) | BIT(BAR_3) | BIT(BAR_5), |
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.bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4), |
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.align = SZ_16K, |
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}; |
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static const struct pci_epc_features * |
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keembay_pcie_get_features(struct dw_pcie_ep *ep) |
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{ |
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return &keembay_pcie_epc_features; |
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} |
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static const struct dw_pcie_ep_ops keembay_pcie_ep_ops = { |
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.ep_init = keembay_pcie_ep_init, |
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.raise_irq = keembay_pcie_ep_raise_irq, |
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.get_features = keembay_pcie_get_features, |
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}; |
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static const struct dw_pcie_host_ops keembay_pcie_host_ops = { |
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}; |
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static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie, |
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struct platform_device *pdev) |
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{ |
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struct dw_pcie *pci = &pcie->pci; |
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struct pcie_port *pp = &pci->pp; |
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struct device *dev = &pdev->dev; |
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u32 val; |
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int ret; |
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pp->ops = &keembay_pcie_host_ops; |
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pp->msi_irq = -ENODEV; |
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ret = keembay_pcie_setup_msi_irq(pcie); |
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if (ret) |
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return ret; |
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pcie->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); |
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if (IS_ERR(pcie->reset)) |
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return PTR_ERR(pcie->reset); |
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ret = keembay_pcie_probe_clocks(pcie); |
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if (ret) |
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return ret; |
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val = readl(pcie->apb_base + PCIE_REGS_PCIE_PHY_CNTL); |
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val |= PHY0_SRAM_BYPASS; |
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writel(val, pcie->apb_base + PCIE_REGS_PCIE_PHY_CNTL); |
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writel(PCIE_DEVICE_TYPE, pcie->apb_base + PCIE_REGS_PCIE_CFG); |
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ret = keembay_pcie_pll_init(pcie); |
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if (ret) |
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return ret; |
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val = readl(pcie->apb_base + PCIE_REGS_PCIE_CFG); |
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writel(val | PCIE_RSTN, pcie->apb_base + PCIE_REGS_PCIE_CFG); |
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keembay_ep_reset_deassert(pcie); |
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ret = dw_pcie_host_init(pp); |
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if (ret) { |
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keembay_ep_reset_assert(pcie); |
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dev_err(dev, "Failed to initialize host: %d\n", ret); |
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return ret; |
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} |
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val = readl(pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE); |
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if (IS_ENABLED(CONFIG_PCI_MSI)) |
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val |= MSI_CTRL_INT_EN; |
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writel(val, pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE); |
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return 0; |
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} |
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static int keembay_pcie_probe(struct platform_device *pdev) |
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{ |
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const struct keembay_pcie_of_data *data; |
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struct device *dev = &pdev->dev; |
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struct keembay_pcie *pcie; |
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struct dw_pcie *pci; |
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enum dw_pcie_device_mode mode; |
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data = device_get_match_data(dev); |
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if (!data) |
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return -ENODEV; |
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mode = (enum dw_pcie_device_mode)data->mode; |
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); |
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if (!pcie) |
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return -ENOMEM; |
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pci = &pcie->pci; |
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pci->dev = dev; |
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pci->ops = &keembay_pcie_ops; |
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pcie->mode = mode; |
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pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); |
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if (IS_ERR(pcie->apb_base)) |
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return PTR_ERR(pcie->apb_base); |
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platform_set_drvdata(pdev, pcie); |
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switch (pcie->mode) { |
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case DW_PCIE_RC_TYPE: |
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if (!IS_ENABLED(CONFIG_PCIE_KEEMBAY_HOST)) |
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return -ENODEV; |
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return keembay_pcie_add_pcie_port(pcie, pdev); |
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case DW_PCIE_EP_TYPE: |
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if (!IS_ENABLED(CONFIG_PCIE_KEEMBAY_EP)) |
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return -ENODEV; |
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pci->ep.ops = &keembay_pcie_ep_ops; |
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return dw_pcie_ep_init(&pci->ep); |
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default: |
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dev_err(dev, "Invalid device type %d\n", pcie->mode); |
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return -ENODEV; |
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} |
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} |
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static const struct keembay_pcie_of_data keembay_pcie_rc_of_data = { |
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.mode = DW_PCIE_RC_TYPE, |
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}; |
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static const struct keembay_pcie_of_data keembay_pcie_ep_of_data = { |
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.mode = DW_PCIE_EP_TYPE, |
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}; |
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static const struct of_device_id keembay_pcie_of_match[] = { |
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{ |
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.compatible = "intel,keembay-pcie", |
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.data = &keembay_pcie_rc_of_data, |
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}, |
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{ |
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.compatible = "intel,keembay-pcie-ep", |
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.data = &keembay_pcie_ep_of_data, |
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}, |
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{} |
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}; |
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static struct platform_driver keembay_pcie_driver = { |
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.driver = { |
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.name = "keembay-pcie", |
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.of_match_table = keembay_pcie_of_match, |
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.suppress_bind_attrs = true, |
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}, |
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.probe = keembay_pcie_probe, |
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}; |
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builtin_platform_driver(keembay_pcie_driver);
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