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309 lines
9.2 KiB
309 lines
9.2 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* FU740 DesignWare PCIe Controller integration |
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* Copyright (C) 2019-2021 SiFive, Inc. |
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* Paul Walmsley |
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* Greentime Hu |
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* |
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* Based in part on the i.MX6 PCIe host controller shim which is: |
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* |
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* Copyright (C) 2013 Kosagi |
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* https://www.kosagi.com |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/gpio.h> |
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#include <linux/gpio/consumer.h> |
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#include <linux/kernel.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/platform_device.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/resource.h> |
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#include <linux/types.h> |
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#include <linux/interrupt.h> |
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#include <linux/iopoll.h> |
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#include <linux/reset.h> |
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#include "pcie-designware.h" |
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#define to_fu740_pcie(x) dev_get_drvdata((x)->dev) |
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struct fu740_pcie { |
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struct dw_pcie pci; |
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void __iomem *mgmt_base; |
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struct gpio_desc *reset; |
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struct gpio_desc *pwren; |
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struct clk *pcie_aux; |
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struct reset_control *rst; |
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}; |
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#define SIFIVE_DEVICESRESETREG 0x28 |
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#define PCIEX8MGMT_PERST_N 0x0 |
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#define PCIEX8MGMT_APP_LTSSM_ENABLE 0x10 |
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#define PCIEX8MGMT_APP_HOLD_PHY_RST 0x18 |
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#define PCIEX8MGMT_DEVICE_TYPE 0x708 |
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#define PCIEX8MGMT_PHY0_CR_PARA_ADDR 0x860 |
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#define PCIEX8MGMT_PHY0_CR_PARA_RD_EN 0x870 |
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#define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA 0x878 |
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#define PCIEX8MGMT_PHY0_CR_PARA_SEL 0x880 |
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#define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA 0x888 |
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#define PCIEX8MGMT_PHY0_CR_PARA_WR_EN 0x890 |
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#define PCIEX8MGMT_PHY0_CR_PARA_ACK 0x898 |
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#define PCIEX8MGMT_PHY1_CR_PARA_ADDR 0x8a0 |
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#define PCIEX8MGMT_PHY1_CR_PARA_RD_EN 0x8b0 |
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#define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA 0x8b8 |
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#define PCIEX8MGMT_PHY1_CR_PARA_SEL 0x8c0 |
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#define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA 0x8c8 |
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#define PCIEX8MGMT_PHY1_CR_PARA_WR_EN 0x8d0 |
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#define PCIEX8MGMT_PHY1_CR_PARA_ACK 0x8d8 |
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#define PCIEX8MGMT_PHY_CDR_TRACK_EN BIT(0) |
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#define PCIEX8MGMT_PHY_LOS_THRSHLD BIT(5) |
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#define PCIEX8MGMT_PHY_TERM_EN BIT(9) |
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#define PCIEX8MGMT_PHY_TERM_ACDC BIT(10) |
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#define PCIEX8MGMT_PHY_EN BIT(11) |
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#define PCIEX8MGMT_PHY_INIT_VAL (PCIEX8MGMT_PHY_CDR_TRACK_EN|\ |
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PCIEX8MGMT_PHY_LOS_THRSHLD|\ |
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PCIEX8MGMT_PHY_TERM_EN|\ |
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PCIEX8MGMT_PHY_TERM_ACDC|\ |
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PCIEX8MGMT_PHY_EN) |
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#define PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 0x1008 |
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#define PCIEX8MGMT_PHY_LANE_OFF 0x100 |
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#define PCIEX8MGMT_PHY_LANE0_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 0) |
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#define PCIEX8MGMT_PHY_LANE1_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 1) |
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#define PCIEX8MGMT_PHY_LANE2_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 2) |
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#define PCIEX8MGMT_PHY_LANE3_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 3) |
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static void fu740_pcie_assert_reset(struct fu740_pcie *afp) |
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{ |
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/* Assert PERST_N GPIO */ |
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gpiod_set_value_cansleep(afp->reset, 0); |
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/* Assert controller PERST_N */ |
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writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N); |
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} |
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static void fu740_pcie_deassert_reset(struct fu740_pcie *afp) |
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{ |
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/* Deassert controller PERST_N */ |
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writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PERST_N); |
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/* Deassert PERST_N GPIO */ |
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gpiod_set_value_cansleep(afp->reset, 1); |
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} |
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static void fu740_pcie_power_on(struct fu740_pcie *afp) |
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{ |
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gpiod_set_value_cansleep(afp->pwren, 1); |
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/* |
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* Ensure that PERST has been asserted for at least 100 ms. |
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* Section 2.2 of PCI Express Card Electromechanical Specification |
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* Revision 3.0 |
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*/ |
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msleep(100); |
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} |
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static void fu740_pcie_drive_reset(struct fu740_pcie *afp) |
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{ |
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fu740_pcie_assert_reset(afp); |
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fu740_pcie_power_on(afp); |
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fu740_pcie_deassert_reset(afp); |
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} |
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static void fu740_phyregwrite(const uint8_t phy, const uint16_t addr, |
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const uint16_t wrdata, struct fu740_pcie *afp) |
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{ |
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struct device *dev = afp->pci.dev; |
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void __iomem *phy_cr_para_addr; |
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void __iomem *phy_cr_para_wr_data; |
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void __iomem *phy_cr_para_wr_en; |
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void __iomem *phy_cr_para_ack; |
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int ret, val; |
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/* Setup */ |
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if (phy) { |
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phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ADDR; |
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phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_DATA; |
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phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_EN; |
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phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ACK; |
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} else { |
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phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ADDR; |
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phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_DATA; |
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phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_EN; |
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phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ACK; |
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} |
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writel_relaxed(addr, phy_cr_para_addr); |
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writel_relaxed(wrdata, phy_cr_para_wr_data); |
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writel_relaxed(1, phy_cr_para_wr_en); |
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/* Wait for wait_idle */ |
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ret = readl_poll_timeout(phy_cr_para_ack, val, val, 10, 5000); |
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if (ret) |
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dev_warn(dev, "Wait for wait_idle state failed!\n"); |
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/* Clear */ |
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writel_relaxed(0, phy_cr_para_wr_en); |
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/* Wait for ~wait_idle */ |
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ret = readl_poll_timeout(phy_cr_para_ack, val, !val, 10, 5000); |
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if (ret) |
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dev_warn(dev, "Wait for !wait_idle state failed!\n"); |
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} |
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static void fu740_pcie_init_phy(struct fu740_pcie *afp) |
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{ |
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/* Enable phy cr_para_sel interfaces */ |
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writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL); |
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writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL); |
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/* |
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* Wait 10 cr_para cycles to guarantee that the registers are ready |
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* to be edited. |
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*/ |
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ndelay(10); |
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/* Set PHY AC termination mode */ |
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fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); |
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fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); |
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fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); |
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fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); |
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fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); |
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fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); |
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fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); |
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fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); |
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} |
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static int fu740_pcie_start_link(struct dw_pcie *pci) |
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{ |
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struct device *dev = pci->dev; |
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struct fu740_pcie *afp = dev_get_drvdata(dev); |
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/* Enable LTSSM */ |
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writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE); |
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return 0; |
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} |
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static int fu740_pcie_host_init(struct pcie_port *pp) |
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{ |
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
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struct fu740_pcie *afp = to_fu740_pcie(pci); |
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struct device *dev = pci->dev; |
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int ret; |
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/* Power on reset */ |
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fu740_pcie_drive_reset(afp); |
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/* Enable pcieauxclk */ |
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ret = clk_prepare_enable(afp->pcie_aux); |
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if (ret) { |
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dev_err(dev, "unable to enable pcie_aux clock\n"); |
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return ret; |
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} |
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/* |
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* Assert hold_phy_rst (hold the controller LTSSM in reset after |
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* power_up_rst_n for register programming with cr_para) |
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*/ |
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writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST); |
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/* Deassert power_up_rst_n */ |
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ret = reset_control_deassert(afp->rst); |
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if (ret) { |
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dev_err(dev, "unable to deassert pcie_power_up_rst_n\n"); |
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return ret; |
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} |
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fu740_pcie_init_phy(afp); |
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/* Disable pcieauxclk */ |
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clk_disable_unprepare(afp->pcie_aux); |
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/* Clear hold_phy_rst */ |
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writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST); |
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/* Enable pcieauxclk */ |
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ret = clk_prepare_enable(afp->pcie_aux); |
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/* Set RC mode */ |
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writel_relaxed(0x4, afp->mgmt_base + PCIEX8MGMT_DEVICE_TYPE); |
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return 0; |
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} |
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static const struct dw_pcie_host_ops fu740_pcie_host_ops = { |
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.host_init = fu740_pcie_host_init, |
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}; |
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static const struct dw_pcie_ops dw_pcie_ops = { |
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.start_link = fu740_pcie_start_link, |
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}; |
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static int fu740_pcie_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct dw_pcie *pci; |
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struct fu740_pcie *afp; |
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afp = devm_kzalloc(dev, sizeof(*afp), GFP_KERNEL); |
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if (!afp) |
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return -ENOMEM; |
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pci = &afp->pci; |
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pci->dev = dev; |
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pci->ops = &dw_pcie_ops; |
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pci->pp.ops = &fu740_pcie_host_ops; |
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/* SiFive specific region: mgmt */ |
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afp->mgmt_base = devm_platform_ioremap_resource_byname(pdev, "mgmt"); |
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if (IS_ERR(afp->mgmt_base)) |
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return PTR_ERR(afp->mgmt_base); |
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/* Fetch GPIOs */ |
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afp->reset = devm_gpiod_get_optional(dev, "reset-gpios", GPIOD_OUT_LOW); |
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if (IS_ERR(afp->reset)) |
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return dev_err_probe(dev, PTR_ERR(afp->reset), "unable to get reset-gpios\n"); |
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afp->pwren = devm_gpiod_get_optional(dev, "pwren-gpios", GPIOD_OUT_LOW); |
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if (IS_ERR(afp->pwren)) |
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return dev_err_probe(dev, PTR_ERR(afp->pwren), "unable to get pwren-gpios\n"); |
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/* Fetch clocks */ |
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afp->pcie_aux = devm_clk_get(dev, "pcie_aux"); |
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if (IS_ERR(afp->pcie_aux)) |
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return dev_err_probe(dev, PTR_ERR(afp->pcie_aux), |
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"pcie_aux clock source missing or invalid\n"); |
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/* Fetch reset */ |
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afp->rst = devm_reset_control_get_exclusive(dev, NULL); |
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if (IS_ERR(afp->rst)) |
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return dev_err_probe(dev, PTR_ERR(afp->rst), "unable to get reset\n"); |
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platform_set_drvdata(pdev, afp); |
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return dw_pcie_host_init(&pci->pp); |
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} |
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static void fu740_pcie_shutdown(struct platform_device *pdev) |
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{ |
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struct fu740_pcie *afp = platform_get_drvdata(pdev); |
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/* Bring down link, so bootloader gets clean state in case of reboot */ |
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fu740_pcie_assert_reset(afp); |
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} |
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static const struct of_device_id fu740_pcie_of_match[] = { |
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{ .compatible = "sifive,fu740-pcie", }, |
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{}, |
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}; |
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static struct platform_driver fu740_pcie_driver = { |
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.driver = { |
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.name = "fu740-pcie", |
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.of_match_table = fu740_pcie_of_match, |
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.suppress_bind_attrs = true, |
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}, |
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.probe = fu740_pcie_probe, |
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.shutdown = fu740_pcie_shutdown, |
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}; |
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builtin_platform_driver(fu740_pcie_driver);
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