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792 lines
20 KiB
792 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Synopsys DesignWare PCIe Endpoint controller driver |
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* |
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* Copyright (C) 2017 Texas Instruments |
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* Author: Kishon Vijay Abraham I <[email protected]> |
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*/ |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include "pcie-designware.h" |
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#include <linux/pci-epc.h> |
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#include <linux/pci-epf.h> |
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#include "../../pci.h" |
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void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) |
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{ |
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struct pci_epc *epc = ep->epc; |
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pci_epc_linkup(epc); |
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} |
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EXPORT_SYMBOL_GPL(dw_pcie_ep_linkup); |
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void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) |
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{ |
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struct pci_epc *epc = ep->epc; |
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pci_epc_init_notify(epc); |
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} |
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EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify); |
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struct dw_pcie_ep_func * |
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dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no) |
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{ |
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struct dw_pcie_ep_func *ep_func; |
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list_for_each_entry(ep_func, &ep->func_list, list) { |
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if (ep_func->func_no == func_no) |
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return ep_func; |
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} |
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return NULL; |
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} |
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static unsigned int dw_pcie_ep_func_select(struct dw_pcie_ep *ep, u8 func_no) |
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{ |
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unsigned int func_offset = 0; |
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if (ep->ops->func_conf_select) |
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func_offset = ep->ops->func_conf_select(ep, func_no); |
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return func_offset; |
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} |
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static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no, |
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enum pci_barno bar, int flags) |
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{ |
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u32 reg; |
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unsigned int func_offset = 0; |
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struct dw_pcie_ep *ep = &pci->ep; |
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func_offset = dw_pcie_ep_func_select(ep, func_no); |
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reg = func_offset + PCI_BASE_ADDRESS_0 + (4 * bar); |
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dw_pcie_dbi_ro_wr_en(pci); |
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dw_pcie_writel_dbi2(pci, reg, 0x0); |
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dw_pcie_writel_dbi(pci, reg, 0x0); |
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if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
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dw_pcie_writel_dbi2(pci, reg + 4, 0x0); |
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dw_pcie_writel_dbi(pci, reg + 4, 0x0); |
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} |
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dw_pcie_dbi_ro_wr_dis(pci); |
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} |
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void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) |
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{ |
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u8 func_no, funcs; |
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funcs = pci->ep.epc->max_functions; |
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for (func_no = 0; func_no < funcs; func_no++) |
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__dw_pcie_ep_reset_bar(pci, func_no, bar, 0); |
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} |
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static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie_ep *ep, u8 func_no, |
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u8 cap_ptr, u8 cap) |
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{ |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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unsigned int func_offset = 0; |
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u8 cap_id, next_cap_ptr; |
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u16 reg; |
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if (!cap_ptr) |
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return 0; |
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func_offset = dw_pcie_ep_func_select(ep, func_no); |
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reg = dw_pcie_readw_dbi(pci, func_offset + cap_ptr); |
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cap_id = (reg & 0x00ff); |
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if (cap_id > PCI_CAP_ID_MAX) |
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return 0; |
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if (cap_id == cap) |
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return cap_ptr; |
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next_cap_ptr = (reg & 0xff00) >> 8; |
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return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap); |
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} |
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static u8 dw_pcie_ep_find_capability(struct dw_pcie_ep *ep, u8 func_no, u8 cap) |
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{ |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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unsigned int func_offset = 0; |
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u8 next_cap_ptr; |
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u16 reg; |
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func_offset = dw_pcie_ep_func_select(ep, func_no); |
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reg = dw_pcie_readw_dbi(pci, func_offset + PCI_CAPABILITY_LIST); |
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next_cap_ptr = (reg & 0x00ff); |
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return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap); |
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} |
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static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, |
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struct pci_epf_header *hdr) |
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{ |
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struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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unsigned int func_offset = 0; |
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func_offset = dw_pcie_ep_func_select(ep, func_no); |
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dw_pcie_dbi_ro_wr_en(pci); |
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dw_pcie_writew_dbi(pci, func_offset + PCI_VENDOR_ID, hdr->vendorid); |
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dw_pcie_writew_dbi(pci, func_offset + PCI_DEVICE_ID, hdr->deviceid); |
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dw_pcie_writeb_dbi(pci, func_offset + PCI_REVISION_ID, hdr->revid); |
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dw_pcie_writeb_dbi(pci, func_offset + PCI_CLASS_PROG, hdr->progif_code); |
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dw_pcie_writew_dbi(pci, func_offset + PCI_CLASS_DEVICE, |
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hdr->subclass_code | hdr->baseclass_code << 8); |
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dw_pcie_writeb_dbi(pci, func_offset + PCI_CACHE_LINE_SIZE, |
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hdr->cache_line_size); |
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dw_pcie_writew_dbi(pci, func_offset + PCI_SUBSYSTEM_VENDOR_ID, |
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hdr->subsys_vendor_id); |
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dw_pcie_writew_dbi(pci, func_offset + PCI_SUBSYSTEM_ID, hdr->subsys_id); |
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dw_pcie_writeb_dbi(pci, func_offset + PCI_INTERRUPT_PIN, |
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hdr->interrupt_pin); |
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dw_pcie_dbi_ro_wr_dis(pci); |
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return 0; |
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} |
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static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, |
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enum pci_barno bar, dma_addr_t cpu_addr, |
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enum dw_pcie_as_type as_type) |
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{ |
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int ret; |
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u32 free_win; |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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free_win = find_first_zero_bit(ep->ib_window_map, pci->num_ib_windows); |
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if (free_win >= pci->num_ib_windows) { |
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dev_err(pci->dev, "No free inbound window\n"); |
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return -EINVAL; |
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} |
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ret = dw_pcie_prog_inbound_atu(pci, func_no, free_win, bar, cpu_addr, |
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as_type); |
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if (ret < 0) { |
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dev_err(pci->dev, "Failed to program IB window\n"); |
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return ret; |
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} |
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ep->bar_to_atu[bar] = free_win; |
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set_bit(free_win, ep->ib_window_map); |
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return 0; |
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} |
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static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no, |
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phys_addr_t phys_addr, |
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u64 pci_addr, size_t size) |
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{ |
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u32 free_win; |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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free_win = find_first_zero_bit(ep->ob_window_map, pci->num_ob_windows); |
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if (free_win >= pci->num_ob_windows) { |
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dev_err(pci->dev, "No free outbound window\n"); |
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return -EINVAL; |
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} |
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dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM, |
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phys_addr, pci_addr, size); |
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set_bit(free_win, ep->ob_window_map); |
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ep->outbound_addr[free_win] = phys_addr; |
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return 0; |
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} |
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static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, |
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struct pci_epf_bar *epf_bar) |
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{ |
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struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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enum pci_barno bar = epf_bar->barno; |
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u32 atu_index = ep->bar_to_atu[bar]; |
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__dw_pcie_ep_reset_bar(pci, func_no, bar, epf_bar->flags); |
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dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND); |
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clear_bit(atu_index, ep->ib_window_map); |
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ep->epf_bar[bar] = NULL; |
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} |
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static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, |
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struct pci_epf_bar *epf_bar) |
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{ |
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int ret; |
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struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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enum pci_barno bar = epf_bar->barno; |
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size_t size = epf_bar->size; |
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int flags = epf_bar->flags; |
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enum dw_pcie_as_type as_type; |
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u32 reg; |
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unsigned int func_offset = 0; |
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func_offset = dw_pcie_ep_func_select(ep, func_no); |
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reg = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset; |
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if (!(flags & PCI_BASE_ADDRESS_SPACE)) |
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as_type = DW_PCIE_AS_MEM; |
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else |
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as_type = DW_PCIE_AS_IO; |
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ret = dw_pcie_ep_inbound_atu(ep, func_no, bar, |
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epf_bar->phys_addr, as_type); |
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if (ret) |
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return ret; |
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dw_pcie_dbi_ro_wr_en(pci); |
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dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1)); |
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dw_pcie_writel_dbi(pci, reg, flags); |
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if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
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dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1)); |
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dw_pcie_writel_dbi(pci, reg + 4, 0); |
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} |
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ep->epf_bar[bar] = epf_bar; |
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dw_pcie_dbi_ro_wr_dis(pci); |
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return 0; |
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} |
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static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr, |
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u32 *atu_index) |
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{ |
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u32 index; |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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for (index = 0; index < pci->num_ob_windows; index++) { |
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if (ep->outbound_addr[index] != addr) |
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continue; |
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*atu_index = index; |
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return 0; |
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} |
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return -EINVAL; |
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} |
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static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, |
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phys_addr_t addr) |
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{ |
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int ret; |
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u32 atu_index; |
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struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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ret = dw_pcie_find_index(ep, addr, &atu_index); |
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if (ret < 0) |
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return; |
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dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND); |
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clear_bit(atu_index, ep->ob_window_map); |
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} |
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static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, |
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phys_addr_t addr, u64 pci_addr, size_t size) |
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{ |
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int ret; |
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struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size); |
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if (ret) { |
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dev_err(pci->dev, "Failed to enable address\n"); |
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return ret; |
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} |
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return 0; |
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} |
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static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no) |
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{ |
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struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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u32 val, reg; |
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unsigned int func_offset = 0; |
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struct dw_pcie_ep_func *ep_func; |
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ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); |
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if (!ep_func || !ep_func->msi_cap) |
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return -EINVAL; |
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func_offset = dw_pcie_ep_func_select(ep, func_no); |
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reg = ep_func->msi_cap + func_offset + PCI_MSI_FLAGS; |
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val = dw_pcie_readw_dbi(pci, reg); |
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if (!(val & PCI_MSI_FLAGS_ENABLE)) |
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return -EINVAL; |
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val = (val & PCI_MSI_FLAGS_QSIZE) >> 4; |
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return val; |
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} |
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static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no, |
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u8 interrupts) |
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{ |
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struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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u32 val, reg; |
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unsigned int func_offset = 0; |
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struct dw_pcie_ep_func *ep_func; |
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ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); |
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if (!ep_func || !ep_func->msi_cap) |
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return -EINVAL; |
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func_offset = dw_pcie_ep_func_select(ep, func_no); |
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reg = ep_func->msi_cap + func_offset + PCI_MSI_FLAGS; |
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val = dw_pcie_readw_dbi(pci, reg); |
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val &= ~PCI_MSI_FLAGS_QMASK; |
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val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK; |
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dw_pcie_dbi_ro_wr_en(pci); |
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dw_pcie_writew_dbi(pci, reg, val); |
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dw_pcie_dbi_ro_wr_dis(pci); |
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return 0; |
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} |
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static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no) |
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{ |
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struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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u32 val, reg; |
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unsigned int func_offset = 0; |
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struct dw_pcie_ep_func *ep_func; |
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ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); |
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if (!ep_func || !ep_func->msix_cap) |
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return -EINVAL; |
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func_offset = dw_pcie_ep_func_select(ep, func_no); |
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reg = ep_func->msix_cap + func_offset + PCI_MSIX_FLAGS; |
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val = dw_pcie_readw_dbi(pci, reg); |
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if (!(val & PCI_MSIX_FLAGS_ENABLE)) |
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return -EINVAL; |
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val &= PCI_MSIX_FLAGS_QSIZE; |
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return val; |
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} |
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static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no, |
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u16 interrupts, enum pci_barno bir, u32 offset) |
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{ |
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struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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u32 val, reg; |
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unsigned int func_offset = 0; |
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struct dw_pcie_ep_func *ep_func; |
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ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); |
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if (!ep_func || !ep_func->msix_cap) |
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return -EINVAL; |
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dw_pcie_dbi_ro_wr_en(pci); |
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func_offset = dw_pcie_ep_func_select(ep, func_no); |
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reg = ep_func->msix_cap + func_offset + PCI_MSIX_FLAGS; |
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val = dw_pcie_readw_dbi(pci, reg); |
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val &= ~PCI_MSIX_FLAGS_QSIZE; |
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val |= interrupts; |
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dw_pcie_writew_dbi(pci, reg, val); |
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reg = ep_func->msix_cap + func_offset + PCI_MSIX_TABLE; |
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val = offset | bir; |
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dw_pcie_writel_dbi(pci, reg, val); |
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reg = ep_func->msix_cap + func_offset + PCI_MSIX_PBA; |
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val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir; |
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dw_pcie_writel_dbi(pci, reg, val); |
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dw_pcie_dbi_ro_wr_dis(pci); |
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return 0; |
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} |
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static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, |
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enum pci_epc_irq_type type, u16 interrupt_num) |
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{ |
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struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
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if (!ep->ops->raise_irq) |
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return -EINVAL; |
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return ep->ops->raise_irq(ep, func_no, type, interrupt_num); |
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} |
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static void dw_pcie_ep_stop(struct pci_epc *epc) |
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{ |
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struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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if (pci->ops && pci->ops->stop_link) |
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pci->ops->stop_link(pci); |
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} |
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static int dw_pcie_ep_start(struct pci_epc *epc) |
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{ |
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struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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if (!pci->ops || !pci->ops->start_link) |
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return -EINVAL; |
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return pci->ops->start_link(pci); |
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} |
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static const struct pci_epc_features* |
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dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) |
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{ |
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struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
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if (!ep->ops->get_features) |
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return NULL; |
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return ep->ops->get_features(ep); |
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} |
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static const struct pci_epc_ops epc_ops = { |
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.write_header = dw_pcie_ep_write_header, |
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.set_bar = dw_pcie_ep_set_bar, |
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.clear_bar = dw_pcie_ep_clear_bar, |
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.map_addr = dw_pcie_ep_map_addr, |
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.unmap_addr = dw_pcie_ep_unmap_addr, |
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.set_msi = dw_pcie_ep_set_msi, |
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.get_msi = dw_pcie_ep_get_msi, |
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.set_msix = dw_pcie_ep_set_msix, |
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.get_msix = dw_pcie_ep_get_msix, |
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.raise_irq = dw_pcie_ep_raise_irq, |
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.start = dw_pcie_ep_start, |
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.stop = dw_pcie_ep_stop, |
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.get_features = dw_pcie_ep_get_features, |
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}; |
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int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no) |
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{ |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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struct device *dev = pci->dev; |
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dev_err(dev, "EP cannot trigger legacy IRQs\n"); |
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return -EINVAL; |
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} |
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int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, |
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u8 interrupt_num) |
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{ |
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
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struct dw_pcie_ep_func *ep_func; |
|
struct pci_epc *epc = ep->epc; |
|
unsigned int aligned_offset; |
|
unsigned int func_offset = 0; |
|
u16 msg_ctrl, msg_data; |
|
u32 msg_addr_lower, msg_addr_upper, reg; |
|
u64 msg_addr; |
|
bool has_upper; |
|
int ret; |
|
|
|
ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); |
|
if (!ep_func || !ep_func->msi_cap) |
|
return -EINVAL; |
|
|
|
func_offset = dw_pcie_ep_func_select(ep, func_no); |
|
|
|
/* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */ |
|
reg = ep_func->msi_cap + func_offset + PCI_MSI_FLAGS; |
|
msg_ctrl = dw_pcie_readw_dbi(pci, reg); |
|
has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT); |
|
reg = ep_func->msi_cap + func_offset + PCI_MSI_ADDRESS_LO; |
|
msg_addr_lower = dw_pcie_readl_dbi(pci, reg); |
|
if (has_upper) { |
|
reg = ep_func->msi_cap + func_offset + PCI_MSI_ADDRESS_HI; |
|
msg_addr_upper = dw_pcie_readl_dbi(pci, reg); |
|
reg = ep_func->msi_cap + func_offset + PCI_MSI_DATA_64; |
|
msg_data = dw_pcie_readw_dbi(pci, reg); |
|
} else { |
|
msg_addr_upper = 0; |
|
reg = ep_func->msi_cap + func_offset + PCI_MSI_DATA_32; |
|
msg_data = dw_pcie_readw_dbi(pci, reg); |
|
} |
|
aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1); |
|
msg_addr = ((u64)msg_addr_upper) << 32 | |
|
(msg_addr_lower & ~aligned_offset); |
|
ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, |
|
epc->mem->window.page_size); |
|
if (ret) |
|
return ret; |
|
|
|
writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset); |
|
|
|
dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys); |
|
|
|
return 0; |
|
} |
|
|
|
int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no, |
|
u16 interrupt_num) |
|
{ |
|
struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
|
struct dw_pcie_ep_func *ep_func; |
|
u32 msg_data; |
|
|
|
ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); |
|
if (!ep_func || !ep_func->msix_cap) |
|
return -EINVAL; |
|
|
|
msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) | |
|
(interrupt_num - 1); |
|
|
|
dw_pcie_writel_dbi(pci, PCIE_MSIX_DOORBELL, msg_data); |
|
|
|
return 0; |
|
} |
|
|
|
int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, |
|
u16 interrupt_num) |
|
{ |
|
struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
|
struct dw_pcie_ep_func *ep_func; |
|
struct pci_epf_msix_tbl *msix_tbl; |
|
struct pci_epc *epc = ep->epc; |
|
unsigned int func_offset = 0; |
|
u32 reg, msg_data, vec_ctrl; |
|
unsigned int aligned_offset; |
|
u32 tbl_offset; |
|
u64 msg_addr; |
|
int ret; |
|
u8 bir; |
|
|
|
ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); |
|
if (!ep_func || !ep_func->msix_cap) |
|
return -EINVAL; |
|
|
|
func_offset = dw_pcie_ep_func_select(ep, func_no); |
|
|
|
reg = ep_func->msix_cap + func_offset + PCI_MSIX_TABLE; |
|
tbl_offset = dw_pcie_readl_dbi(pci, reg); |
|
bir = (tbl_offset & PCI_MSIX_TABLE_BIR); |
|
tbl_offset &= PCI_MSIX_TABLE_OFFSET; |
|
|
|
msix_tbl = ep->epf_bar[bir]->addr + tbl_offset; |
|
msg_addr = msix_tbl[(interrupt_num - 1)].msg_addr; |
|
msg_data = msix_tbl[(interrupt_num - 1)].msg_data; |
|
vec_ctrl = msix_tbl[(interrupt_num - 1)].vector_ctrl; |
|
|
|
if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT) { |
|
dev_dbg(pci->dev, "MSI-X entry ctrl set\n"); |
|
return -EPERM; |
|
} |
|
|
|
aligned_offset = msg_addr & (epc->mem->window.page_size - 1); |
|
ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, |
|
epc->mem->window.page_size); |
|
if (ret) |
|
return ret; |
|
|
|
writel(msg_data, ep->msi_mem + aligned_offset); |
|
|
|
dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys); |
|
|
|
return 0; |
|
} |
|
|
|
void dw_pcie_ep_exit(struct dw_pcie_ep *ep) |
|
{ |
|
struct pci_epc *epc = ep->epc; |
|
|
|
pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, |
|
epc->mem->window.page_size); |
|
|
|
pci_epc_mem_exit(epc); |
|
} |
|
|
|
static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) |
|
{ |
|
u32 header; |
|
int pos = PCI_CFG_SPACE_SIZE; |
|
|
|
while (pos) { |
|
header = dw_pcie_readl_dbi(pci, pos); |
|
if (PCI_EXT_CAP_ID(header) == cap) |
|
return pos; |
|
|
|
pos = PCI_EXT_CAP_NEXT(header); |
|
if (!pos) |
|
break; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) |
|
{ |
|
struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
|
unsigned int offset; |
|
unsigned int nbars; |
|
u8 hdr_type; |
|
u32 reg; |
|
int i; |
|
|
|
hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE) & |
|
PCI_HEADER_TYPE_MASK; |
|
if (hdr_type != PCI_HEADER_TYPE_NORMAL) { |
|
dev_err(pci->dev, |
|
"PCIe controller is not set to EP mode (hdr_type:0x%x)!\n", |
|
hdr_type); |
|
return -EIO; |
|
} |
|
|
|
offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); |
|
|
|
dw_pcie_dbi_ro_wr_en(pci); |
|
|
|
if (offset) { |
|
reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); |
|
nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> |
|
PCI_REBAR_CTRL_NBAR_SHIFT; |
|
|
|
for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) |
|
dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0); |
|
} |
|
|
|
dw_pcie_setup(pci); |
|
dw_pcie_dbi_ro_wr_dis(pci); |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete); |
|
|
|
int dw_pcie_ep_init(struct dw_pcie_ep *ep) |
|
{ |
|
int ret; |
|
void *addr; |
|
u8 func_no; |
|
struct resource *res; |
|
struct pci_epc *epc; |
|
struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
|
struct device *dev = pci->dev; |
|
struct platform_device *pdev = to_platform_device(dev); |
|
struct device_node *np = dev->of_node; |
|
const struct pci_epc_features *epc_features; |
|
struct dw_pcie_ep_func *ep_func; |
|
|
|
INIT_LIST_HEAD(&ep->func_list); |
|
|
|
if (!pci->dbi_base) { |
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); |
|
pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); |
|
if (IS_ERR(pci->dbi_base)) |
|
return PTR_ERR(pci->dbi_base); |
|
} |
|
|
|
if (!pci->dbi_base2) { |
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); |
|
if (!res) |
|
pci->dbi_base2 = pci->dbi_base + SZ_4K; |
|
else { |
|
pci->dbi_base2 = devm_pci_remap_cfg_resource(dev, res); |
|
if (IS_ERR(pci->dbi_base2)) |
|
return PTR_ERR(pci->dbi_base2); |
|
} |
|
} |
|
|
|
dw_pcie_iatu_detect(pci); |
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); |
|
if (!res) |
|
return -EINVAL; |
|
|
|
ep->phys_base = res->start; |
|
ep->addr_size = resource_size(res); |
|
|
|
ep->ib_window_map = devm_kcalloc(dev, |
|
BITS_TO_LONGS(pci->num_ib_windows), |
|
sizeof(long), |
|
GFP_KERNEL); |
|
if (!ep->ib_window_map) |
|
return -ENOMEM; |
|
|
|
ep->ob_window_map = devm_kcalloc(dev, |
|
BITS_TO_LONGS(pci->num_ob_windows), |
|
sizeof(long), |
|
GFP_KERNEL); |
|
if (!ep->ob_window_map) |
|
return -ENOMEM; |
|
|
|
addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t), |
|
GFP_KERNEL); |
|
if (!addr) |
|
return -ENOMEM; |
|
ep->outbound_addr = addr; |
|
|
|
if (pci->link_gen < 1) |
|
pci->link_gen = of_pci_get_max_link_speed(np); |
|
|
|
epc = devm_pci_epc_create(dev, &epc_ops); |
|
if (IS_ERR(epc)) { |
|
dev_err(dev, "Failed to create epc device\n"); |
|
return PTR_ERR(epc); |
|
} |
|
|
|
ep->epc = epc; |
|
epc_set_drvdata(epc, ep); |
|
|
|
ret = of_property_read_u8(np, "max-functions", &epc->max_functions); |
|
if (ret < 0) |
|
epc->max_functions = 1; |
|
|
|
for (func_no = 0; func_no < epc->max_functions; func_no++) { |
|
ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL); |
|
if (!ep_func) |
|
return -ENOMEM; |
|
|
|
ep_func->func_no = func_no; |
|
ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no, |
|
PCI_CAP_ID_MSI); |
|
ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no, |
|
PCI_CAP_ID_MSIX); |
|
|
|
list_add_tail(&ep_func->list, &ep->func_list); |
|
} |
|
|
|
if (ep->ops->ep_init) |
|
ep->ops->ep_init(ep); |
|
|
|
ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, |
|
ep->page_size); |
|
if (ret < 0) { |
|
dev_err(dev, "Failed to initialize address space\n"); |
|
return ret; |
|
} |
|
|
|
ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, |
|
epc->mem->window.page_size); |
|
if (!ep->msi_mem) { |
|
dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
if (ep->ops->get_features) { |
|
epc_features = ep->ops->get_features(ep); |
|
if (epc_features->core_init_notifier) |
|
return 0; |
|
} |
|
|
|
return dw_pcie_ep_init_complete(ep); |
|
} |
|
EXPORT_SYMBOL_GPL(dw_pcie_ep_init);
|
|
|