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445 lines
11 KiB
445 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* PCIe host controller driver for Samsung Exynos SoCs |
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* |
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* Copyright (C) 2013-2020 Samsung Electronics Co., Ltd. |
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* https://www.samsung.com |
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* |
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* Author: Jingoo Han <[email protected]> |
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* Jaehoon Chung <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/of_device.h> |
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#include <linux/pci.h> |
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#include <linux/platform_device.h> |
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#include <linux/phy/phy.h> |
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#include <linux/regulator/consumer.h> |
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#include "pcie-designware.h" |
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#define to_exynos_pcie(x) dev_get_drvdata((x)->dev) |
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/* PCIe ELBI registers */ |
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#define PCIE_IRQ_PULSE 0x000 |
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#define IRQ_INTA_ASSERT BIT(0) |
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#define IRQ_INTB_ASSERT BIT(2) |
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#define IRQ_INTC_ASSERT BIT(4) |
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#define IRQ_INTD_ASSERT BIT(6) |
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#define PCIE_IRQ_LEVEL 0x004 |
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#define PCIE_IRQ_SPECIAL 0x008 |
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#define PCIE_IRQ_EN_PULSE 0x00c |
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#define PCIE_IRQ_EN_LEVEL 0x010 |
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#define PCIE_IRQ_EN_SPECIAL 0x014 |
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#define PCIE_SW_WAKE 0x018 |
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#define PCIE_BUS_EN BIT(1) |
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#define PCIE_CORE_RESET 0x01c |
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#define PCIE_CORE_RESET_ENABLE BIT(0) |
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#define PCIE_STICKY_RESET 0x020 |
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#define PCIE_NONSTICKY_RESET 0x024 |
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#define PCIE_APP_INIT_RESET 0x028 |
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#define PCIE_APP_LTSSM_ENABLE 0x02c |
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#define PCIE_ELBI_RDLH_LINKUP 0x074 |
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#define PCIE_ELBI_XMLH_LINKUP BIT(4) |
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#define PCIE_ELBI_LTSSM_ENABLE 0x1 |
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#define PCIE_ELBI_SLV_AWMISC 0x11c |
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#define PCIE_ELBI_SLV_ARMISC 0x120 |
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#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) |
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struct exynos_pcie { |
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struct dw_pcie pci; |
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void __iomem *elbi_base; |
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struct clk *clk; |
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struct clk *bus_clk; |
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struct phy *phy; |
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struct regulator_bulk_data supplies[2]; |
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}; |
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static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep) |
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{ |
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struct device *dev = ep->pci.dev; |
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int ret; |
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ret = clk_prepare_enable(ep->clk); |
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if (ret) { |
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dev_err(dev, "cannot enable pcie rc clock"); |
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return ret; |
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} |
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ret = clk_prepare_enable(ep->bus_clk); |
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if (ret) { |
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dev_err(dev, "cannot enable pcie bus clock"); |
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goto err_bus_clk; |
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} |
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return 0; |
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err_bus_clk: |
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clk_disable_unprepare(ep->clk); |
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return ret; |
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} |
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static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep) |
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{ |
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clk_disable_unprepare(ep->bus_clk); |
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clk_disable_unprepare(ep->clk); |
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} |
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static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) |
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{ |
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writel(val, base + reg); |
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} |
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static u32 exynos_pcie_readl(void __iomem *base, u32 reg) |
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{ |
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return readl(base + reg); |
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} |
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static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on) |
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{ |
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u32 val; |
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val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC); |
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if (on) |
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val |= PCIE_ELBI_SLV_DBI_ENABLE; |
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else |
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val &= ~PCIE_ELBI_SLV_DBI_ENABLE; |
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exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC); |
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} |
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static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on) |
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{ |
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u32 val; |
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val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC); |
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if (on) |
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val |= PCIE_ELBI_SLV_DBI_ENABLE; |
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else |
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val &= ~PCIE_ELBI_SLV_DBI_ENABLE; |
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exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC); |
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} |
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static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep) |
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{ |
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u32 val; |
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val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); |
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val &= ~PCIE_CORE_RESET_ENABLE; |
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exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); |
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exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET); |
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exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET); |
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} |
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static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep) |
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{ |
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u32 val; |
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val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); |
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val |= PCIE_CORE_RESET_ENABLE; |
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exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); |
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exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET); |
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exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET); |
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exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET); |
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exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET); |
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} |
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static int exynos_pcie_start_link(struct dw_pcie *pci) |
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{ |
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struct exynos_pcie *ep = to_exynos_pcie(pci); |
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u32 val; |
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val = exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE); |
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val &= ~PCIE_BUS_EN; |
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exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE); |
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/* assert LTSSM enable */ |
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exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE, |
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PCIE_APP_LTSSM_ENABLE); |
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return 0; |
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} |
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static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep) |
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{ |
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u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE); |
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exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE); |
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} |
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static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) |
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{ |
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struct exynos_pcie *ep = arg; |
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exynos_pcie_clear_irq_pulse(ep); |
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return IRQ_HANDLED; |
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} |
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static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) |
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{ |
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u32 val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | |
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IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; |
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exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE); |
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exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL); |
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exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_SPECIAL); |
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} |
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static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, |
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u32 reg, size_t size) |
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{ |
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struct exynos_pcie *ep = to_exynos_pcie(pci); |
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u32 val; |
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exynos_pcie_sideband_dbi_r_mode(ep, true); |
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dw_pcie_read(base + reg, size, &val); |
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exynos_pcie_sideband_dbi_r_mode(ep, false); |
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return val; |
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} |
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static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, |
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u32 reg, size_t size, u32 val) |
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{ |
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struct exynos_pcie *ep = to_exynos_pcie(pci); |
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exynos_pcie_sideband_dbi_w_mode(ep, true); |
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dw_pcie_write(base + reg, size, val); |
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exynos_pcie_sideband_dbi_w_mode(ep, false); |
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} |
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static int exynos_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *val) |
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{ |
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struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); |
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if (PCI_SLOT(devfn)) { |
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*val = ~0; |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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} |
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*val = dw_pcie_read_dbi(pci, where, size); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int exynos_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 val) |
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{ |
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struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); |
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if (PCI_SLOT(devfn)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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dw_pcie_write_dbi(pci, where, size, val); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static struct pci_ops exynos_pci_ops = { |
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.read = exynos_pcie_rd_own_conf, |
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.write = exynos_pcie_wr_own_conf, |
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}; |
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static int exynos_pcie_link_up(struct dw_pcie *pci) |
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{ |
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struct exynos_pcie *ep = to_exynos_pcie(pci); |
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u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); |
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return (val & PCIE_ELBI_XMLH_LINKUP); |
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} |
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static int exynos_pcie_host_init(struct pcie_port *pp) |
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{ |
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
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struct exynos_pcie *ep = to_exynos_pcie(pci); |
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pp->bridge->ops = &exynos_pci_ops; |
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exynos_pcie_assert_core_reset(ep); |
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phy_reset(ep->phy); |
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phy_power_on(ep->phy); |
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phy_init(ep->phy); |
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exynos_pcie_deassert_core_reset(ep); |
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exynos_pcie_enable_irq_pulse(ep); |
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return 0; |
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} |
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static const struct dw_pcie_host_ops exynos_pcie_host_ops = { |
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.host_init = exynos_pcie_host_init, |
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}; |
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static int exynos_add_pcie_port(struct exynos_pcie *ep, |
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struct platform_device *pdev) |
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{ |
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struct dw_pcie *pci = &ep->pci; |
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struct pcie_port *pp = &pci->pp; |
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struct device *dev = &pdev->dev; |
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int ret; |
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pp->irq = platform_get_irq(pdev, 0); |
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if (pp->irq < 0) |
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return pp->irq; |
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ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler, |
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IRQF_SHARED, "exynos-pcie", ep); |
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if (ret) { |
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dev_err(dev, "failed to request irq\n"); |
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return ret; |
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} |
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pp->ops = &exynos_pcie_host_ops; |
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pp->msi_irq = -ENODEV; |
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ret = dw_pcie_host_init(pp); |
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if (ret) { |
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dev_err(dev, "failed to initialize host\n"); |
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return ret; |
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} |
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return 0; |
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} |
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static const struct dw_pcie_ops dw_pcie_ops = { |
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.read_dbi = exynos_pcie_read_dbi, |
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.write_dbi = exynos_pcie_write_dbi, |
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.link_up = exynos_pcie_link_up, |
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.start_link = exynos_pcie_start_link, |
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}; |
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static int exynos_pcie_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct exynos_pcie *ep; |
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struct device_node *np = dev->of_node; |
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int ret; |
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ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); |
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if (!ep) |
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return -ENOMEM; |
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ep->pci.dev = dev; |
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ep->pci.ops = &dw_pcie_ops; |
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ep->phy = devm_of_phy_get(dev, np, NULL); |
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if (IS_ERR(ep->phy)) |
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return PTR_ERR(ep->phy); |
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/* External Local Bus interface (ELBI) registers */ |
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ep->elbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi"); |
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if (IS_ERR(ep->elbi_base)) |
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return PTR_ERR(ep->elbi_base); |
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ep->clk = devm_clk_get(dev, "pcie"); |
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if (IS_ERR(ep->clk)) { |
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dev_err(dev, "Failed to get pcie rc clock\n"); |
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return PTR_ERR(ep->clk); |
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} |
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ep->bus_clk = devm_clk_get(dev, "pcie_bus"); |
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if (IS_ERR(ep->bus_clk)) { |
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dev_err(dev, "Failed to get pcie bus clock\n"); |
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return PTR_ERR(ep->bus_clk); |
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} |
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ep->supplies[0].supply = "vdd18"; |
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ep->supplies[1].supply = "vdd10"; |
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ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ep->supplies), |
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ep->supplies); |
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if (ret) |
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return ret; |
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ret = exynos_pcie_init_clk_resources(ep); |
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if (ret) |
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return ret; |
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ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); |
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if (ret) |
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return ret; |
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platform_set_drvdata(pdev, ep); |
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ret = exynos_add_pcie_port(ep, pdev); |
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if (ret < 0) |
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goto fail_probe; |
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return 0; |
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fail_probe: |
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phy_exit(ep->phy); |
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exynos_pcie_deinit_clk_resources(ep); |
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regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); |
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return ret; |
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} |
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static int __exit exynos_pcie_remove(struct platform_device *pdev) |
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{ |
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struct exynos_pcie *ep = platform_get_drvdata(pdev); |
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dw_pcie_host_deinit(&ep->pci.pp); |
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exynos_pcie_assert_core_reset(ep); |
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phy_power_off(ep->phy); |
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phy_exit(ep->phy); |
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exynos_pcie_deinit_clk_resources(ep); |
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regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); |
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return 0; |
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} |
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static int __maybe_unused exynos_pcie_suspend_noirq(struct device *dev) |
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{ |
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struct exynos_pcie *ep = dev_get_drvdata(dev); |
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exynos_pcie_assert_core_reset(ep); |
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phy_power_off(ep->phy); |
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phy_exit(ep->phy); |
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regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); |
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return 0; |
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} |
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static int __maybe_unused exynos_pcie_resume_noirq(struct device *dev) |
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{ |
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struct exynos_pcie *ep = dev_get_drvdata(dev); |
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struct dw_pcie *pci = &ep->pci; |
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struct pcie_port *pp = &pci->pp; |
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int ret; |
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ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); |
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if (ret) |
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return ret; |
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/* exynos_pcie_host_init controls ep->phy */ |
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exynos_pcie_host_init(pp); |
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dw_pcie_setup_rc(pp); |
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exynos_pcie_start_link(pci); |
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return dw_pcie_wait_for_link(pci); |
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} |
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static const struct dev_pm_ops exynos_pcie_pm_ops = { |
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos_pcie_suspend_noirq, |
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exynos_pcie_resume_noirq) |
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}; |
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static const struct of_device_id exynos_pcie_of_match[] = { |
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{ .compatible = "samsung,exynos5433-pcie", }, |
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{ }, |
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}; |
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static struct platform_driver exynos_pcie_driver = { |
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.probe = exynos_pcie_probe, |
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.remove = __exit_p(exynos_pcie_remove), |
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.driver = { |
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.name = "exynos-pcie", |
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.of_match_table = exynos_pcie_of_match, |
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.pm = &exynos_pcie_pm_ops, |
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}, |
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}; |
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module_platform_driver(exynos_pcie_driver); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_DEVICE_TABLE(of, exynos_pcie_of_match);
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