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1069 lines
31 KiB
1069 lines
31 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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** DINO manager |
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** |
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** (c) Copyright 1999 Red Hat Software |
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** (c) Copyright 1999 SuSE GmbH |
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** (c) Copyright 1999,2000 Hewlett-Packard Company |
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** (c) Copyright 2000 Grant Grundler |
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** (c) Copyright 2006-2019 Helge Deller |
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** |
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** |
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** This module provides access to Dino PCI bus (config/IOport spaces) |
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** and helps manage Dino IRQ lines. |
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** |
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** Dino interrupt handling is a bit complicated. |
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** Dino always writes to the broadcast EIR via irr0 for now. |
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** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!) |
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** Only one processor interrupt is used for the 11 IRQ line |
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** inputs to dino. |
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** |
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** The different between Built-in Dino and Card-Mode |
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** dino is in chip initialization and pci device initialization. |
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** |
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** Linux drivers can only use Card-Mode Dino if pci devices I/O port |
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** BARs are configured and used by the driver. Programming MMIO address |
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** requires substantial knowledge of available Host I/O address ranges |
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** is currently not supported. Port/Config accessor functions are the |
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** same. "BIOS" differences are handled within the existing routines. |
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*/ |
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|
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/* Changes : |
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** 2001-06-14 : Clement Moyroud ([email protected]) |
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** - added support for the integrated RS232. |
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*/ |
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|
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/* |
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** TODO: create a virtual address for each Dino HPA. |
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** GSC code might be able to do this since IODC data tells us |
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** how many pages are used. PCI subsystem could (must?) do this |
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** for PCI drivers devices which implement/use MMIO registers. |
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*/ |
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#include <linux/delay.h> |
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#include <linux/types.h> |
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/ioport.h> |
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#include <linux/slab.h> |
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#include <linux/interrupt.h> /* for struct irqaction */ |
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#include <linux/spinlock.h> /* for spinlock_t and prototypes */ |
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#include <asm/pdc.h> |
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#include <asm/page.h> |
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#include <asm/io.h> |
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#include <asm/hardware.h> |
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#include "gsc.h" |
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#include "iommu.h" |
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#undef DINO_DEBUG |
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#ifdef DINO_DEBUG |
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#define DBG(x...) printk(x) |
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#else |
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#define DBG(x...) |
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#endif |
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/* |
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** Config accessor functions only pass in the 8-bit bus number |
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** and not the 8-bit "PCI Segment" number. Each Dino will be |
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** assigned a PCI bus number based on "when" it's discovered. |
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** |
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** The "secondary" bus number is set to this before calling |
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** pci_scan_bus(). If any PPB's are present, the scan will |
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** discover them and update the "secondary" and "subordinate" |
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** fields in Dino's pci_bus structure. |
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** |
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** Changes in the configuration *will* result in a different |
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** bus number for each dino. |
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*/ |
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#define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA) |
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#define is_cujo(id) ((id)->hversion == 0x682) |
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#define DINO_IAR0 0x004 |
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#define DINO_IODC_ADDR 0x008 |
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#define DINO_IODC_DATA_0 0x008 |
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#define DINO_IODC_DATA_1 0x008 |
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#define DINO_IRR0 0x00C |
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#define DINO_IAR1 0x010 |
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#define DINO_IRR1 0x014 |
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#define DINO_IMR 0x018 |
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#define DINO_IPR 0x01C |
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#define DINO_TOC_ADDR 0x020 |
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#define DINO_ICR 0x024 |
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#define DINO_ILR 0x028 |
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#define DINO_IO_COMMAND 0x030 |
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#define DINO_IO_STATUS 0x034 |
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#define DINO_IO_CONTROL 0x038 |
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#define DINO_IO_GSC_ERR_RESP 0x040 |
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#define DINO_IO_ERR_INFO 0x044 |
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#define DINO_IO_PCI_ERR_RESP 0x048 |
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#define DINO_IO_FBB_EN 0x05c |
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#define DINO_IO_ADDR_EN 0x060 |
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#define DINO_PCI_ADDR 0x064 |
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#define DINO_CONFIG_DATA 0x068 |
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#define DINO_IO_DATA 0x06c |
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#define DINO_MEM_DATA 0x070 /* Dino 3.x only */ |
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#define DINO_GSC2X_CONFIG 0x7b4 |
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#define DINO_GMASK 0x800 |
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#define DINO_PAMR 0x804 |
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#define DINO_PAPR 0x808 |
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#define DINO_DAMODE 0x80c |
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#define DINO_PCICMD 0x810 |
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#define DINO_PCISTS 0x814 |
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#define DINO_MLTIM 0x81c |
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#define DINO_BRDG_FEAT 0x820 |
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#define DINO_PCIROR 0x824 |
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#define DINO_PCIWOR 0x828 |
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#define DINO_TLTIM 0x830 |
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#define DINO_IRQS 11 /* bits 0-10 are architected */ |
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#define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ |
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#define DINO_LOCAL_IRQS (DINO_IRQS+1) |
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#define DINO_MASK_IRQ(x) (1<<(x)) |
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#define PCIINTA 0x001 |
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#define PCIINTB 0x002 |
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#define PCIINTC 0x004 |
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#define PCIINTD 0x008 |
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#define PCIINTE 0x010 |
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#define PCIINTF 0x020 |
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#define GSCEXTINT 0x040 |
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/* #define xxx 0x080 - bit 7 is "default" */ |
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/* #define xxx 0x100 - bit 8 not used */ |
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/* #define xxx 0x200 - bit 9 not used */ |
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#define RS232INT 0x400 |
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struct dino_device |
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{ |
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struct pci_hba_data hba; /* 'C' inheritance - must be first */ |
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spinlock_t dinosaur_pen; |
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unsigned long txn_addr; /* EIR addr to generate interrupt */ |
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u32 txn_data; /* EIR data assign to each dino */ |
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u32 imr; /* IRQ's which are enabled */ |
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int global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */ |
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#ifdef DINO_DEBUG |
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unsigned int dino_irr0; /* save most recent IRQ line stat */ |
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#endif |
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}; |
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static inline struct dino_device *DINO_DEV(struct pci_hba_data *hba) |
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{ |
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return container_of(hba, struct dino_device, hba); |
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} |
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/* Check if PCI device is behind a Card-mode Dino. */ |
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static int pci_dev_is_behind_card_dino(struct pci_dev *dev) |
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{ |
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struct dino_device *dino_dev; |
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dino_dev = DINO_DEV(parisc_walk_tree(dev->bus->bridge)); |
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return is_card_dino(&dino_dev->hba.dev->id); |
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} |
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/* |
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* Dino Configuration Space Accessor Functions |
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*/ |
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#define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos))) |
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/* |
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* keep the current highest bus count to assist in allocating busses. This |
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* tries to keep a global bus count total so that when we discover an |
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* entirely new bus, it can be given a unique bus number. |
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*/ |
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static int dino_current_bus = 0; |
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static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where, |
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int size, u32 *val) |
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{ |
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struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); |
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u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start; |
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u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); |
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void __iomem *base_addr = d->hba.base_addr; |
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unsigned long flags; |
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DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where, |
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size); |
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spin_lock_irqsave(&d->dinosaur_pen, flags); |
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/* tell HW which CFG address */ |
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__raw_writel(v, base_addr + DINO_PCI_ADDR); |
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/* generate cfg read cycle */ |
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if (size == 1) { |
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*val = readb(base_addr + DINO_CONFIG_DATA + (where & 3)); |
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} else if (size == 2) { |
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*val = readw(base_addr + DINO_CONFIG_DATA + (where & 2)); |
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} else if (size == 4) { |
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*val = readl(base_addr + DINO_CONFIG_DATA); |
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} |
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spin_unlock_irqrestore(&d->dinosaur_pen, flags); |
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return 0; |
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} |
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/* |
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* Dino address stepping "feature": |
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* When address stepping, Dino attempts to drive the bus one cycle too soon |
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* even though the type of cycle (config vs. MMIO) might be different. |
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* The read of Ven/Prod ID is harmless and avoids Dino's address stepping. |
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*/ |
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static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where, |
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int size, u32 val) |
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{ |
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struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); |
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u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start; |
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u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); |
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void __iomem *base_addr = d->hba.base_addr; |
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unsigned long flags; |
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DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where, |
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size); |
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spin_lock_irqsave(&d->dinosaur_pen, flags); |
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/* avoid address stepping feature */ |
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__raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR); |
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__raw_readl(base_addr + DINO_CONFIG_DATA); |
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/* tell HW which CFG address */ |
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__raw_writel(v, base_addr + DINO_PCI_ADDR); |
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/* generate cfg read cycle */ |
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if (size == 1) { |
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writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3)); |
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} else if (size == 2) { |
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writew(val, base_addr + DINO_CONFIG_DATA + (where & 2)); |
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} else if (size == 4) { |
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writel(val, base_addr + DINO_CONFIG_DATA); |
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} |
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spin_unlock_irqrestore(&d->dinosaur_pen, flags); |
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return 0; |
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} |
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static struct pci_ops dino_cfg_ops = { |
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.read = dino_cfg_read, |
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.write = dino_cfg_write, |
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}; |
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/* |
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* Dino "I/O Port" Space Accessor Functions |
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* |
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* Many PCI devices don't require use of I/O port space (eg Tulip, |
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* NCR720) since they export the same registers to both MMIO and |
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* I/O port space. Performance is going to stink if drivers use |
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* I/O port instead of MMIO. |
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*/ |
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#define DINO_PORT_IN(type, size, mask) \ |
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static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \ |
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{ \ |
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u##size v; \ |
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unsigned long flags; \ |
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spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ |
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/* tell HW which IO Port address */ \ |
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__raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ |
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/* generate I/O PORT read cycle */ \ |
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v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \ |
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spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ |
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return v; \ |
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} |
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DINO_PORT_IN(b, 8, 3) |
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DINO_PORT_IN(w, 16, 2) |
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DINO_PORT_IN(l, 32, 0) |
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#define DINO_PORT_OUT(type, size, mask) \ |
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static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ |
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{ \ |
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unsigned long flags; \ |
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spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ |
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/* tell HW which IO port address */ \ |
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__raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ |
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/* generate cfg write cycle */ \ |
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write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \ |
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spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ |
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} |
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DINO_PORT_OUT(b, 8, 3) |
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DINO_PORT_OUT(w, 16, 2) |
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DINO_PORT_OUT(l, 32, 0) |
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static struct pci_port_ops dino_port_ops = { |
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.inb = dino_in8, |
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.inw = dino_in16, |
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.inl = dino_in32, |
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.outb = dino_out8, |
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.outw = dino_out16, |
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.outl = dino_out32 |
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}; |
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static void dino_mask_irq(struct irq_data *d) |
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{ |
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struct dino_device *dino_dev = irq_data_get_irq_chip_data(d); |
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int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS); |
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DBG(KERN_WARNING "%s(0x%px, %d)\n", __func__, dino_dev, d->irq); |
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/* Clear the matching bit in the IMR register */ |
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dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq)); |
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__raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); |
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} |
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static void dino_unmask_irq(struct irq_data *d) |
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{ |
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struct dino_device *dino_dev = irq_data_get_irq_chip_data(d); |
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int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS); |
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u32 tmp; |
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DBG(KERN_WARNING "%s(0x%px, %d)\n", __func__, dino_dev, d->irq); |
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/* |
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** clear pending IRQ bits |
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** |
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** This does NOT change ILR state! |
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** See comment below for ILR usage. |
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*/ |
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__raw_readl(dino_dev->hba.base_addr+DINO_IPR); |
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/* set the matching bit in the IMR register */ |
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dino_dev->imr |= DINO_MASK_IRQ(local_irq); /* used in dino_isr() */ |
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__raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); |
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|
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/* Emulate "Level Triggered" Interrupt |
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** Basically, a driver is blowing it if the IRQ line is asserted |
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** while the IRQ is disabled. But tulip.c seems to do that.... |
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** Give 'em a kluge award and a nice round of applause! |
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** |
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** The gsc_write will generate an interrupt which invokes dino_isr(). |
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** dino_isr() will read IPR and find nothing. But then catch this |
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** when it also checks ILR. |
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*/ |
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tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR); |
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if (tmp & DINO_MASK_IRQ(local_irq)) { |
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DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n", |
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__func__, tmp); |
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gsc_writel(dino_dev->txn_data, dino_dev->txn_addr); |
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} |
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} |
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static struct irq_chip dino_interrupt_type = { |
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.name = "GSC-PCI", |
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.irq_unmask = dino_unmask_irq, |
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.irq_mask = dino_mask_irq, |
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}; |
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/* |
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* Handle a Processor interrupt generated by Dino. |
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* |
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* ilr_loop counter is a kluge to prevent a "stuck" IRQ line from |
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* wedging the CPU. Could be removed or made optional at some point. |
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*/ |
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static irqreturn_t dino_isr(int irq, void *intr_dev) |
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{ |
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struct dino_device *dino_dev = intr_dev; |
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u32 mask; |
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int ilr_loop = 100; |
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|
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/* read and acknowledge pending interrupts */ |
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#ifdef DINO_DEBUG |
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dino_dev->dino_irr0 = |
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#endif |
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mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK; |
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if (mask == 0) |
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return IRQ_NONE; |
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ilr_again: |
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do { |
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int local_irq = __ffs(mask); |
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int irq = dino_dev->global_irq[local_irq]; |
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DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n", |
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__func__, irq, intr_dev, mask); |
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generic_handle_irq(irq); |
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mask &= ~DINO_MASK_IRQ(local_irq); |
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} while (mask); |
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|
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/* Support for level triggered IRQ lines. |
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** |
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** Dropping this support would make this routine *much* faster. |
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** But since PCI requires level triggered IRQ line to share lines... |
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** device drivers may assume lines are level triggered (and not |
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** edge triggered like EISA/ISA can be). |
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*/ |
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mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr; |
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if (mask) { |
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if (--ilr_loop > 0) |
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goto ilr_again; |
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pr_warn_ratelimited("Dino 0x%px: stuck interrupt %d\n", |
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dino_dev->hba.base_addr, mask); |
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} |
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return IRQ_HANDLED; |
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} |
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|
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static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp) |
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{ |
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int irq = gsc_assign_irq(&dino_interrupt_type, dino); |
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if (irq == NO_IRQ) |
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return; |
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*irqp = irq; |
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dino->global_irq[local_irq] = irq; |
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} |
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static void dino_choose_irq(struct parisc_device *dev, void *ctrl) |
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{ |
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int irq; |
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struct dino_device *dino = ctrl; |
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|
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switch (dev->id.sversion) { |
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case 0x00084: irq = 8; break; /* PS/2 */ |
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case 0x0008c: irq = 10; break; /* RS232 */ |
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case 0x00096: irq = 8; break; /* PS/2 */ |
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default: return; /* Unknown */ |
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} |
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dino_assign_irq(dino, irq, &dev->irq); |
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} |
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|
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/* |
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* Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop ([email protected]) |
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* (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...) |
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*/ |
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static void quirk_cirrus_cardbus(struct pci_dev *dev) |
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{ |
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u8 new_irq = dev->irq - 1; |
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printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n", |
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pci_name(dev), dev->irq, new_irq); |
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dev->irq = new_irq; |
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} |
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DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus ); |
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#ifdef CONFIG_TULIP |
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static void pci_fixup_tulip(struct pci_dev *dev) |
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{ |
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if (!pci_dev_is_behind_card_dino(dev)) |
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return; |
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if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) |
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return; |
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pr_warn("%s: HP HSC-PCI Cards with card-mode Dino not yet supported.\n", |
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pci_name(dev)); |
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/* Disable this card by zeroing the PCI resources */ |
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memset(&dev->resource[0], 0, sizeof(dev->resource[0])); |
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memset(&dev->resource[1], 0, sizeof(dev->resource[1])); |
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} |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_DEC, PCI_ANY_ID, pci_fixup_tulip); |
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#endif /* CONFIG_TULIP */ |
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static void __init |
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dino_bios_init(void) |
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{ |
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DBG("dino_bios_init\n"); |
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} |
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|
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/* |
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* dino_card_setup - Set up the memory space for a Dino in card mode. |
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* @bus: the bus under this dino |
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* |
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* Claim an 8MB chunk of unused IO space and call the generic PCI routines |
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* to set up the addresses of the devices on this bus. |
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*/ |
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#define _8MB 0x00800000UL |
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static void __init |
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dino_card_setup(struct pci_bus *bus, void __iomem *base_addr) |
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{ |
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int i; |
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struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); |
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struct resource *res; |
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char name[128]; |
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int size; |
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|
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res = &dino_dev->hba.lmmio_space; |
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res->flags = IORESOURCE_MEM; |
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size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", |
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dev_name(bus->bridge)); |
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res->name = kmalloc(size+1, GFP_KERNEL); |
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if(res->name) |
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strcpy((char *)res->name, name); |
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else |
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res->name = dino_dev->hba.lmmio_space.name; |
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|
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|
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if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB, |
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F_EXTEND(0xf0000000UL) | _8MB, |
|
F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) { |
|
struct pci_dev *dev, *tmp; |
|
|
|
printk(KERN_ERR "Dino: cannot attach bus %s\n", |
|
dev_name(bus->bridge)); |
|
/* kill the bus, we can't do anything with it */ |
|
list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) { |
|
list_del(&dev->bus_list); |
|
} |
|
|
|
return; |
|
} |
|
bus->resource[1] = res; |
|
bus->resource[0] = &(dino_dev->hba.io_space); |
|
|
|
/* Now tell dino what range it has */ |
|
for (i = 1; i < 31; i++) { |
|
if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB))) |
|
break; |
|
} |
|
DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n", |
|
i, res->start, base_addr + DINO_IO_ADDR_EN); |
|
__raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN); |
|
} |
|
|
|
static void __init |
|
dino_card_fixup(struct pci_dev *dev) |
|
{ |
|
u32 irq_pin; |
|
|
|
/* |
|
** REVISIT: card-mode PCI-PCI expansion chassis do exist. |
|
** Not sure they were ever productized. |
|
** Die here since we'll die later in dino_inb() anyway. |
|
*/ |
|
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { |
|
panic("Card-Mode Dino: PCI-PCI Bridge not supported\n"); |
|
} |
|
|
|
/* |
|
** Set Latency Timer to 0xff (not a shared bus) |
|
** Set CACHELINE_SIZE. |
|
*/ |
|
dino_cfg_write(dev->bus, dev->devfn, |
|
PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4); |
|
|
|
/* |
|
** Program INT_LINE for card-mode devices. |
|
** The cards are hardwired according to this algorithm. |
|
** And it doesn't matter if PPB's are present or not since |
|
** the IRQ lines bypass the PPB. |
|
** |
|
** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range. |
|
** The additional "-1" adjusts for skewing the IRQ<->slot. |
|
*/ |
|
dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin); |
|
dev->irq = pci_swizzle_interrupt_pin(dev, irq_pin) - 1; |
|
|
|
/* Shouldn't really need to do this but it's in case someone tries |
|
** to bypass PCI services and look at the card themselves. |
|
*/ |
|
dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq); |
|
} |
|
|
|
/* The alignment contraints for PCI bridges under dino */ |
|
#define DINO_BRIDGE_ALIGN 0x100000 |
|
|
|
|
|
static void __init |
|
dino_fixup_bus(struct pci_bus *bus) |
|
{ |
|
struct pci_dev *dev; |
|
struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); |
|
|
|
DBG(KERN_WARNING "%s(0x%px) bus %d platform_data 0x%px\n", |
|
__func__, bus, bus->busn_res.start, |
|
bus->bridge->platform_data); |
|
|
|
/* Firmware doesn't set up card-mode dino, so we have to */ |
|
if (is_card_dino(&dino_dev->hba.dev->id)) { |
|
dino_card_setup(bus, dino_dev->hba.base_addr); |
|
} else if (bus->parent) { |
|
int i; |
|
|
|
pci_read_bridge_bases(bus); |
|
|
|
|
|
for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { |
|
if((bus->self->resource[i].flags & |
|
(IORESOURCE_IO | IORESOURCE_MEM)) == 0) |
|
continue; |
|
|
|
if(bus->self->resource[i].flags & IORESOURCE_MEM) { |
|
/* There's a quirk to alignment of |
|
* bridge memory resources: the start |
|
* is the alignment and start-end is |
|
* the size. However, firmware will |
|
* have assigned start and end, so we |
|
* need to take this into account */ |
|
bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN; |
|
bus->self->resource[i].start = DINO_BRIDGE_ALIGN; |
|
|
|
} |
|
|
|
DBG("DEBUG %s assigning %d [%pR]\n", |
|
dev_name(&bus->self->dev), i, |
|
&bus->self->resource[i]); |
|
WARN_ON(pci_assign_resource(bus->self, i)); |
|
DBG("DEBUG %s after assign %d [%pR]\n", |
|
dev_name(&bus->self->dev), i, |
|
&bus->self->resource[i]); |
|
} |
|
} |
|
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list) { |
|
if (is_card_dino(&dino_dev->hba.dev->id)) |
|
dino_card_fixup(dev); |
|
|
|
/* |
|
** P2PB's only have 2 BARs, no IRQs. |
|
** I'd like to just ignore them for now. |
|
*/ |
|
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { |
|
pcibios_init_bridge(dev); |
|
continue; |
|
} |
|
|
|
/* null out the ROM resource if there is one (we don't |
|
* care about an expansion rom on parisc, since it |
|
* usually contains (x86) bios code) */ |
|
dev->resource[PCI_ROM_RESOURCE].flags = 0; |
|
|
|
if(dev->irq == 255) { |
|
|
|
#define DINO_FIX_UNASSIGNED_INTERRUPTS |
|
#ifdef DINO_FIX_UNASSIGNED_INTERRUPTS |
|
|
|
/* This code tries to assign an unassigned |
|
* interrupt. Leave it disabled unless you |
|
* *really* know what you're doing since the |
|
* pin<->interrupt line mapping varies by bus |
|
* and machine */ |
|
|
|
u32 irq_pin; |
|
|
|
dino_cfg_read(dev->bus, dev->devfn, |
|
PCI_INTERRUPT_PIN, 1, &irq_pin); |
|
irq_pin = pci_swizzle_interrupt_pin(dev, irq_pin) - 1; |
|
printk(KERN_WARNING "Device %s has undefined IRQ, " |
|
"setting to %d\n", pci_name(dev), irq_pin); |
|
dino_cfg_write(dev->bus, dev->devfn, |
|
PCI_INTERRUPT_LINE, 1, irq_pin); |
|
dino_assign_irq(dino_dev, irq_pin, &dev->irq); |
|
#else |
|
dev->irq = 65535; |
|
printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev)); |
|
#endif |
|
} else { |
|
/* Adjust INT_LINE for that busses region */ |
|
dino_assign_irq(dino_dev, dev->irq, &dev->irq); |
|
} |
|
} |
|
} |
|
|
|
|
|
static struct pci_bios_ops dino_bios_ops = { |
|
.init = dino_bios_init, |
|
.fixup_bus = dino_fixup_bus |
|
}; |
|
|
|
|
|
/* |
|
* Initialise a DINO controller chip |
|
*/ |
|
static void __init |
|
dino_card_init(struct dino_device *dino_dev) |
|
{ |
|
u32 brdg_feat = 0x00784e05; |
|
unsigned long status; |
|
|
|
status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS); |
|
if (status & 0x0000ff80) { |
|
__raw_writel(0x00000005, |
|
dino_dev->hba.base_addr+DINO_IO_COMMAND); |
|
udelay(1); |
|
} |
|
|
|
__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK); |
|
__raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN); |
|
__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR); |
|
|
|
#if 1 |
|
/* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */ |
|
/* |
|
** PCX-L processors don't support XQL like Dino wants it. |
|
** PCX-L2 ignore XQL signal and it doesn't matter. |
|
*/ |
|
brdg_feat &= ~0x4; /* UXQL */ |
|
#endif |
|
__raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT); |
|
|
|
/* |
|
** Don't enable address decoding until we know which I/O range |
|
** currently is available from the host. Only affects MMIO |
|
** and not I/O port space. |
|
*/ |
|
__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN); |
|
|
|
__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE); |
|
__raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR); |
|
__raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR); |
|
|
|
__raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM); |
|
__raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL); |
|
__raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM); |
|
|
|
/* Disable PAMR before writing PAPR */ |
|
__raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR); |
|
__raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR); |
|
__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR); |
|
|
|
/* |
|
** Dino ERS encourages enabling FBB (0x6f). |
|
** We can't until we know *all* devices below us can support it. |
|
** (Something in device configuration header tells us). |
|
*/ |
|
__raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD); |
|
|
|
/* Somewhere, the PCI spec says give devices 1 second |
|
** to recover from the #RESET being de-asserted. |
|
** Experience shows most devices only need 10ms. |
|
** This short-cut speeds up booting significantly. |
|
*/ |
|
mdelay(pci_post_reset_delay); |
|
} |
|
|
|
static int __init |
|
dino_bridge_init(struct dino_device *dino_dev, const char *name) |
|
{ |
|
unsigned long io_addr; |
|
int result, i, count=0; |
|
struct resource *res, *prevres = NULL; |
|
/* |
|
* Decoding IO_ADDR_EN only works for Built-in Dino |
|
* since PDC has already initialized this. |
|
*/ |
|
|
|
io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN); |
|
if (io_addr == 0) { |
|
printk(KERN_WARNING "%s: No PCI devices enabled.\n", name); |
|
return -ENODEV; |
|
} |
|
|
|
res = &dino_dev->hba.lmmio_space; |
|
for (i = 0; i < 32; i++) { |
|
unsigned long start, end; |
|
|
|
if((io_addr & (1 << i)) == 0) |
|
continue; |
|
|
|
start = F_EXTEND(0xf0000000UL) | (i << 23); |
|
end = start + 8 * 1024 * 1024 - 1; |
|
|
|
DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count, |
|
start, end); |
|
|
|
if(prevres && prevres->end + 1 == start) { |
|
prevres->end = end; |
|
} else { |
|
if(count >= DINO_MAX_LMMIO_RESOURCES) { |
|
printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end); |
|
break; |
|
} |
|
prevres = res; |
|
res->start = start; |
|
res->end = end; |
|
res->flags = IORESOURCE_MEM; |
|
res->name = kmalloc(64, GFP_KERNEL); |
|
if(res->name) |
|
snprintf((char *)res->name, 64, "%s LMMIO %d", |
|
name, count); |
|
res++; |
|
count++; |
|
} |
|
} |
|
|
|
res = &dino_dev->hba.lmmio_space; |
|
|
|
for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { |
|
if(res[i].flags == 0) |
|
break; |
|
|
|
result = ccio_request_resource(dino_dev->hba.dev, &res[i]); |
|
if (result < 0) { |
|
printk(KERN_ERR "%s: failed to claim PCI Bus address " |
|
"space %d (%pR)!\n", name, i, &res[i]); |
|
return result; |
|
} |
|
} |
|
return 0; |
|
} |
|
|
|
static int __init dino_common_init(struct parisc_device *dev, |
|
struct dino_device *dino_dev, const char *name) |
|
{ |
|
int status; |
|
u32 eim; |
|
struct gsc_irq gsc_irq; |
|
struct resource *res; |
|
|
|
pcibios_register_hba(&dino_dev->hba); |
|
|
|
pci_bios = &dino_bios_ops; /* used by pci_scan_bus() */ |
|
pci_port = &dino_port_ops; |
|
|
|
/* |
|
** Note: SMP systems can make use of IRR1/IAR1 registers |
|
** But it won't buy much performance except in very |
|
** specific applications/configurations. Note Dino |
|
** still only has 11 IRQ input lines - just map some of them |
|
** to a different processor. |
|
*/ |
|
dev->irq = gsc_alloc_irq(&gsc_irq); |
|
dino_dev->txn_addr = gsc_irq.txn_addr; |
|
dino_dev->txn_data = gsc_irq.txn_data; |
|
eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data; |
|
|
|
/* |
|
** Dino needs a PA "IRQ" to get a processor's attention. |
|
** arch/parisc/kernel/irq.c returns an EIRR bit. |
|
*/ |
|
if (dev->irq < 0) { |
|
printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name); |
|
return 1; |
|
} |
|
|
|
status = request_irq(dev->irq, dino_isr, 0, name, dino_dev); |
|
if (status) { |
|
printk(KERN_WARNING "%s: request_irq() failed with %d\n", |
|
name, status); |
|
return 1; |
|
} |
|
|
|
/* Support the serial port which is sometimes attached on built-in |
|
* Dino / Cujo chips. |
|
*/ |
|
|
|
gsc_fixup_irqs(dev, dino_dev, dino_choose_irq); |
|
|
|
/* |
|
** This enables DINO to generate interrupts when it sees |
|
** any of its inputs *change*. Just asserting an IRQ |
|
** before it's enabled (ie unmasked) isn't good enough. |
|
*/ |
|
__raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0); |
|
|
|
/* |
|
** Some platforms don't clear Dino's IRR0 register at boot time. |
|
** Reading will clear it now. |
|
*/ |
|
__raw_readl(dino_dev->hba.base_addr+DINO_IRR0); |
|
|
|
/* allocate I/O Port resource region */ |
|
res = &dino_dev->hba.io_space; |
|
if (!is_cujo(&dev->id)) { |
|
res->name = "Dino I/O Port"; |
|
} else { |
|
res->name = "Cujo I/O Port"; |
|
} |
|
res->start = HBA_PORT_BASE(dino_dev->hba.hba_num); |
|
res->end = res->start + (HBA_PORT_SPACE_SIZE - 1); |
|
res->flags = IORESOURCE_IO; /* do not mark it busy ! */ |
|
if (request_resource(&ioport_resource, res) < 0) { |
|
printk(KERN_ERR "%s: request I/O Port region failed " |
|
"0x%lx/%lx (hpa 0x%px)\n", |
|
name, (unsigned long)res->start, (unsigned long)res->end, |
|
dino_dev->hba.base_addr); |
|
return 1; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
#define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL) |
|
#define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL) |
|
#define CUJO_RAVEN_BADPAGE 0x01003000UL |
|
#define CUJO_FIREHAWK_BADPAGE 0x01607000UL |
|
|
|
static const char dino_vers[][4] = { |
|
"2.0", |
|
"2.1", |
|
"3.0", |
|
"3.1" |
|
}; |
|
|
|
static const char cujo_vers[][4] = { |
|
"1.0", |
|
"2.0" |
|
}; |
|
|
|
void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp); |
|
|
|
/* |
|
** Determine if dino should claim this chip (return 0) or not (return 1). |
|
** If so, initialize the chip appropriately (card-mode vs bridge mode). |
|
** Much of the initialization is common though. |
|
*/ |
|
static int __init dino_probe(struct parisc_device *dev) |
|
{ |
|
struct dino_device *dino_dev; // Dino specific control struct |
|
const char *version = "unknown"; |
|
char *name; |
|
int is_cujo = 0; |
|
LIST_HEAD(resources); |
|
struct pci_bus *bus; |
|
unsigned long hpa = dev->hpa.start; |
|
int max; |
|
|
|
name = "Dino"; |
|
if (is_card_dino(&dev->id)) { |
|
version = "3.x (card mode)"; |
|
} else { |
|
if (!is_cujo(&dev->id)) { |
|
if (dev->id.hversion_rev < 4) { |
|
version = dino_vers[dev->id.hversion_rev]; |
|
} |
|
} else { |
|
name = "Cujo"; |
|
is_cujo = 1; |
|
if (dev->id.hversion_rev < 2) { |
|
version = cujo_vers[dev->id.hversion_rev]; |
|
} |
|
} |
|
} |
|
|
|
printk("%s version %s found at 0x%lx\n", name, version, hpa); |
|
|
|
if (!request_mem_region(hpa, PAGE_SIZE, name)) { |
|
printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%lx)!\n", |
|
hpa); |
|
return 1; |
|
} |
|
|
|
/* Check for bugs */ |
|
if (is_cujo && dev->id.hversion_rev == 1) { |
|
#ifdef CONFIG_IOMMU_CCIO |
|
printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n"); |
|
if (hpa == (unsigned long)CUJO_RAVEN_ADDR) { |
|
ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE); |
|
} else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) { |
|
ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE); |
|
} else { |
|
printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa); |
|
} |
|
#endif |
|
} else if (!is_cujo && !is_card_dino(&dev->id) && |
|
dev->id.hversion_rev < 3) { |
|
printk(KERN_WARNING |
|
"The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n" |
|
"data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n" |
|
"Systems shipped after Aug 20, 1997 will not exhibit this problem.\n" |
|
"Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n", |
|
dev->id.hversion_rev); |
|
/* REVISIT: why are C200/C240 listed in the README table but not |
|
** "Models affected"? Could be an omission in the original literature. |
|
*/ |
|
} |
|
|
|
dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL); |
|
if (!dino_dev) { |
|
printk("dino_init_chip - couldn't alloc dino_device\n"); |
|
return 1; |
|
} |
|
|
|
dino_dev->hba.dev = dev; |
|
dino_dev->hba.base_addr = ioremap(hpa, 4096); |
|
dino_dev->hba.lmmio_space_offset = PCI_F_EXTEND; |
|
spin_lock_init(&dino_dev->dinosaur_pen); |
|
dino_dev->hba.iommu = ccio_get_iommu(dev); |
|
|
|
if (is_card_dino(&dev->id)) { |
|
dino_card_init(dino_dev); |
|
} else { |
|
dino_bridge_init(dino_dev, name); |
|
} |
|
|
|
if (dino_common_init(dev, dino_dev, name)) |
|
return 1; |
|
|
|
dev->dev.platform_data = dino_dev; |
|
|
|
pci_add_resource_offset(&resources, &dino_dev->hba.io_space, |
|
HBA_PORT_BASE(dino_dev->hba.hba_num)); |
|
if (dino_dev->hba.lmmio_space.flags) |
|
pci_add_resource_offset(&resources, &dino_dev->hba.lmmio_space, |
|
dino_dev->hba.lmmio_space_offset); |
|
if (dino_dev->hba.elmmio_space.flags) |
|
pci_add_resource_offset(&resources, &dino_dev->hba.elmmio_space, |
|
dino_dev->hba.lmmio_space_offset); |
|
if (dino_dev->hba.gmmio_space.flags) |
|
pci_add_resource(&resources, &dino_dev->hba.gmmio_space); |
|
|
|
dino_dev->hba.bus_num.start = dino_current_bus; |
|
dino_dev->hba.bus_num.end = 255; |
|
dino_dev->hba.bus_num.flags = IORESOURCE_BUS; |
|
pci_add_resource(&resources, &dino_dev->hba.bus_num); |
|
/* |
|
** It's not used to avoid chicken/egg problems |
|
** with configuration accessor functions. |
|
*/ |
|
dino_dev->hba.hba_bus = bus = pci_create_root_bus(&dev->dev, |
|
dino_current_bus, &dino_cfg_ops, NULL, &resources); |
|
if (!bus) { |
|
printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n", |
|
dev_name(&dev->dev), dino_current_bus); |
|
pci_free_resource_list(&resources); |
|
/* increment the bus number in case of duplicates */ |
|
dino_current_bus++; |
|
return 0; |
|
} |
|
|
|
max = pci_scan_child_bus(bus); |
|
pci_bus_update_busn_res_end(bus, max); |
|
|
|
/* This code *depends* on scanning being single threaded |
|
* if it isn't, this global bus number count will fail |
|
*/ |
|
dino_current_bus = max + 1; |
|
pci_bus_assign_resources(bus); |
|
pci_bus_add_devices(bus); |
|
return 0; |
|
} |
|
|
|
/* |
|
* Normally, we would just test sversion. But the Elroy PCI adapter has |
|
* the same sversion as Dino, so we have to check hversion as well. |
|
* Unfortunately, the J2240 PDC reports the wrong hversion for the first |
|
* Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240. |
|
* For card-mode Dino, most machines report an sversion of 9D. But 715 |
|
* and 725 firmware misreport it as 0x08080 for no adequately explained |
|
* reason. |
|
*/ |
|
static const struct parisc_device_id dino_tbl[] __initconst = { |
|
{ HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */ |
|
{ HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */ |
|
{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */ |
|
{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */ |
|
{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */ |
|
{ 0, } |
|
}; |
|
|
|
static struct parisc_driver dino_driver __refdata = { |
|
.name = "dino", |
|
.id_table = dino_tbl, |
|
.probe = dino_probe, |
|
}; |
|
|
|
/* |
|
* One time initialization to let the world know Dino is here. |
|
* This is the only routine which is NOT static. |
|
* Must be called exactly once before pci_init(). |
|
*/ |
|
int __init dino_init(void) |
|
{ |
|
register_parisc_driver(&dino_driver); |
|
return 0; |
|
} |
|
|
|
|