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279 lines
8.4 KiB
279 lines
8.4 KiB
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
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/* Copyright(c) 2018-2019 Realtek Corporation |
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*/ |
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#ifndef __RTW8821C_H__ |
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#define __RTW8821C_H__ |
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#include <asm/byteorder.h> |
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#define RCR_VHT_ACK BIT(26) |
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struct rtw8821ce_efuse { |
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u8 mac_addr[ETH_ALEN]; /* 0xd0 */ |
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u8 vender_id[2]; |
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u8 device_id[2]; |
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u8 sub_vender_id[2]; |
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u8 sub_device_id[2]; |
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u8 pmc[2]; |
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u8 exp_device_cap[2]; |
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u8 msi_cap; |
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u8 ltr_cap; /* 0xe3 */ |
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u8 exp_link_control[2]; |
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u8 link_cap[4]; |
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u8 link_control[2]; |
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u8 serial_number[8]; |
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u8 res0:2; /* 0xf4 */ |
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u8 ltr_en:1; |
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u8 res1:2; |
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u8 obff:2; |
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u8 res2:3; |
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u8 obff_cap:2; |
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u8 res3:4; |
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u8 res4[3]; |
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u8 class_code[3]; |
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u8 pci_pm_L1_2_supp:1; |
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u8 pci_pm_L1_1_supp:1; |
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u8 aspm_pm_L1_2_supp:1; |
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u8 aspm_pm_L1_1_supp:1; |
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u8 L1_pm_substates_supp:1; |
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u8 res5:3; |
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u8 port_common_mode_restore_time; |
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u8 port_t_power_on_scale:2; |
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u8 res6:1; |
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u8 port_t_power_on_value:5; |
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u8 res7; |
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}; |
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struct rtw8821c_efuse { |
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__le16 rtl_id; |
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u8 res0[0x0e]; |
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/* power index for four RF paths */ |
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struct rtw_txpwr_idx txpwr_idx_table[4]; |
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u8 channel_plan; /* 0xb8 */ |
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u8 xtal_k; |
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u8 thermal_meter; |
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u8 iqk_lck; |
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u8 pa_type; /* 0xbc */ |
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u8 lna_type_2g[2]; /* 0xbd */ |
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u8 lna_type_5g[2]; |
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u8 rf_board_option; |
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u8 rf_feature_option; |
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u8 rf_bt_setting; |
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u8 eeprom_version; |
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u8 eeprom_customer_id; |
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u8 tx_bb_swing_setting_2g; |
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u8 tx_bb_swing_setting_5g; |
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u8 tx_pwr_calibrate_rate; |
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u8 rf_antenna_option; /* 0xc9 */ |
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u8 rfe_option; |
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u8 country_code[2]; |
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u8 res[3]; |
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union { |
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struct rtw8821ce_efuse e; |
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}; |
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}; |
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static inline void |
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_rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data) |
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{ |
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/* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */ |
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rtw_write32_mask(rtwdev, addr, mask, data); |
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rtw_write32_mask(rtwdev, addr + 0x200, mask, data); |
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} |
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#define rtw_write32s_mask(rtwdev, addr, mask, data) \ |
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do { \ |
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BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00); \ |
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\ |
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_rtw_write32s_mask(rtwdev, addr, mask, data); \ |
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} while (0) |
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#define BIT_FEN_PCIEA BIT(6) |
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#define WLAN_SLOT_TIME 0x09 |
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#define WLAN_PIFS_TIME 0x19 |
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#define WLAN_SIFS_CCK_CONT_TX 0xA |
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#define WLAN_SIFS_OFDM_CONT_TX 0xE |
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#define WLAN_SIFS_CCK_TRX 0x10 |
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#define WLAN_SIFS_OFDM_TRX 0x10 |
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#define WLAN_VO_TXOP_LIMIT 0x186 |
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#define WLAN_VI_TXOP_LIMIT 0x3BC |
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#define WLAN_RDG_NAV 0x05 |
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#define WLAN_TXOP_NAV 0x1B |
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#define WLAN_CCK_RX_TSF 0x30 |
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#define WLAN_OFDM_RX_TSF 0x30 |
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#define WLAN_TBTT_PROHIBIT 0x04 |
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#define WLAN_TBTT_HOLD_TIME 0x064 |
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#define WLAN_DRV_EARLY_INT 0x04 |
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#define WLAN_BCN_DMA_TIME 0x02 |
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#define WLAN_RX_FILTER0 0x0FFFFFFF |
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#define WLAN_RX_FILTER2 0xFFFF |
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#define WLAN_RCR_CFG 0xE400220E |
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#define WLAN_RXPKT_MAX_SZ 12288 |
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#define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) |
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#define WLAN_AMPDU_MAX_TIME 0x70 |
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#define WLAN_RTS_LEN_TH 0xFF |
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#define WLAN_RTS_TX_TIME_TH 0x08 |
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#define WLAN_MAX_AGG_PKT_LIMIT 0x20 |
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#define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20 |
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#define FAST_EDCA_VO_TH 0x06 |
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#define FAST_EDCA_VI_TH 0x06 |
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#define FAST_EDCA_BE_TH 0x06 |
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#define FAST_EDCA_BK_TH 0x06 |
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#define WLAN_BAR_RETRY_LIMIT 0x01 |
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#define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 |
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#define WLAN_TX_FUNC_CFG1 0x30 |
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#define WLAN_TX_FUNC_CFG2 0x30 |
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#define WLAN_MAC_OPT_NORM_FUNC1 0x98 |
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#define WLAN_MAC_OPT_LB_FUNC1 0x80 |
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#define WLAN_MAC_OPT_FUNC2 0x30810041 |
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#define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ |
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(WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ |
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(WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ |
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(WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) |
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#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ |
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(WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) |
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#define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) |
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#define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) |
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#define WLAN_PRE_TXCNT_TIME_TH 0x1E4 |
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/* phy status page0 */ |
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#define GET_PHY_STAT_P0_PWDB(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8)) |
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#define GET_PHY_STAT_P0_VGA(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(12, 8)) |
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#define GET_PHY_STAT_P0_LNA_L(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(15, 13)) |
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#define GET_PHY_STAT_P0_LNA_H(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x03), BIT(23)) |
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#define BIT_LNA_H_MASK BIT(3) |
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#define BIT_LNA_L_MASK GENMASK(2, 0) |
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/* phy status page1 */ |
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#define GET_PHY_STAT_P1_PWDB_A(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8)) |
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#define GET_PHY_STAT_P1_PWDB_B(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16)) |
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#define GET_PHY_STAT_P1_RF_MODE(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28)) |
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#define GET_PHY_STAT_P1_L_RXSC(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8)) |
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#define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12)) |
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#define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0)) |
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#define GET_PHY_STAT_P1_RXEVM_B(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8)) |
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#define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0)) |
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#define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8)) |
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#define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0)) |
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#define GET_PHY_STAT_P1_RXSNR_B(phy_stat) \ |
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le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8)) |
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#define REG_SYS_CTRL 0x000 |
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#define BIT_FEN_EN BIT(26) |
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#define REG_INIRTS_RATE_SEL 0x0480 |
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#define REG_HTSTFWT 0x800 |
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#define REG_RXPSEL 0x808 |
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#define BIT_RX_PSEL_RST (BIT(28) | BIT(29)) |
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#define REG_TXPSEL 0x80c |
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#define REG_RXCCAMSK 0x814 |
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#define REG_CCASEL 0x82c |
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#define REG_PDMFTH 0x830 |
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#define REG_CCA2ND 0x838 |
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#define REG_L1WT 0x83c |
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#define REG_L1PKWT 0x840 |
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#define REG_MRC 0x850 |
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#define REG_CLKTRK 0x860 |
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#define REG_ADCCLK 0x8ac |
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#define REG_ADC160 0x8c4 |
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#define REG_ADC40 0x8c8 |
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#define REG_CHFIR 0x8f0 |
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#define REG_CDDTXP 0x93c |
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#define REG_TXPSEL1 0x940 |
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#define REG_ACBB0 0x948 |
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#define REG_ACBBRXFIR 0x94c |
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#define REG_ACGG2TBL 0x958 |
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#define REG_FAS 0x9a4 |
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#define REG_RXSB 0xa00 |
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#define REG_ADCINI 0xa04 |
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#define REG_PWRTH 0xa08 |
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#define REG_TXSF2 0xa24 |
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#define REG_TXSF6 0xa28 |
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#define REG_FA_CCK 0xa5c |
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#define REG_RXDESC 0xa2c |
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#define REG_ENTXCCK 0xa80 |
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#define BTG_LNA 0xfc84 |
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#define WLG_LNA 0x7532 |
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#define REG_ENRXCCA 0xa84 |
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#define BTG_CCA 0x0e |
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#define WLG_CCA 0x12 |
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#define REG_PWRTH2 0xaa8 |
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#define REG_CSRATIO 0xaaa |
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#define REG_TXFILTER 0xaac |
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#define REG_CNTRST 0xb58 |
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#define REG_AGCTR_A 0xc08 |
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#define REG_TXSCALE_A 0xc1c |
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#define REG_TXDFIR 0xc20 |
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#define REG_RXIGI_A 0xc50 |
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#define REG_TXAGCIDX 0xc94 |
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#define REG_TRSW 0xca0 |
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#define REG_RFESEL0 0xcb0 |
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#define REG_RFESEL8 0xcb4 |
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#define REG_RFECTL 0xcb8 |
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#define B_BTG_SWITCH BIT(16) |
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#define B_CTRL_SWITCH BIT(18) |
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#define B_WL_SWITCH (BIT(20) | BIT(22)) |
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#define B_WLG_SWITCH BIT(21) |
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#define B_WLA_SWITCH BIT(23) |
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#define REG_RFEINV 0xcbc |
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#define REG_AGCTR_B 0xe08 |
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#define REG_RXIGI_B 0xe50 |
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#define REG_CRC_CCK 0xf04 |
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#define REG_CRC_OFDM 0xf14 |
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#define REG_CRC_HT 0xf10 |
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#define REG_CRC_VHT 0xf0c |
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#define REG_CCA_OFDM 0xf08 |
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#define REG_FA_OFDM 0xf48 |
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#define REG_CCA_CCK 0xfcc |
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#define REG_DMEM_CTRL 0x1080 |
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#define BIT_WL_RST BIT(16) |
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#define REG_ANTWT 0x1904 |
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#define REG_IQKFAILMSK 0x1bf0 |
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#define BIT_MASK_R_RFE_SEL_15 GENMASK(31, 28) |
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#define BIT_SDIO_INT BIT(18) |
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#define BT_CNT_ENABLE 0x1 |
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#define BIT_BCN_QUEUE BIT(3) |
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#define BCN_PRI_EN 0x1 |
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#define PTA_CTRL_PIN 0x66 |
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#define DPDT_CTRL_PIN 0x77 |
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#define ANTDIC_CTRL_PIN 0x88 |
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#define REG_CTRL_TYPE 0x67 |
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#define BIT_CTRL_TYPE1 BIT(5) |
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#define BIT_CTRL_TYPE2 BIT(4) |
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#define CTRL_TYPE_MASK GENMASK(15, 8) |
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#define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) |
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#define RF18_BAND_2G (0) |
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#define RF18_BAND_5G (BIT(16) | BIT(8)) |
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#define RF18_CHANNEL_MASK (MASKBYTE0) |
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#define RF18_RFSI_MASK (BIT(18) | BIT(17)) |
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#define RF18_RFSI_GE (BIT(17)) |
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#define RF18_RFSI_GT (BIT(18)) |
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#define RF18_BW_MASK (BIT(11) | BIT(10)) |
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#define RF18_BW_20M (BIT(11) | BIT(10)) |
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#define RF18_BW_40M (BIT(11)) |
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#define RF18_BW_80M (BIT(10)) |
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#endif
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