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419 lines
13 KiB
419 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright(c) 2009-2014 Realtek Corporation.*/ |
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#include "../wifi.h" |
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#include "phy_common.h" |
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#include "../rtl8723ae/reg.h" |
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#include <linux/module.h> |
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/* These routines are common to RTL8723AE and RTL8723bE */ |
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u32 rtl8723_phy_query_bb_reg(struct ieee80211_hw *hw, |
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u32 regaddr, u32 bitmask) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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u32 returnvalue, originalvalue, bitshift; |
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rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, |
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"regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask); |
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originalvalue = rtl_read_dword(rtlpriv, regaddr); |
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bitshift = rtl8723_phy_calculate_bit_shift(bitmask); |
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returnvalue = (originalvalue & bitmask) >> bitshift; |
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rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, |
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"BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask, |
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regaddr, originalvalue); |
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return returnvalue; |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_query_bb_reg); |
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void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, |
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u32 bitmask, u32 data) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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u32 originalvalue, bitshift; |
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rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, |
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"regaddr(%#x), bitmask(%#x), data(%#x)\n", regaddr, bitmask, |
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data); |
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if (bitmask != MASKDWORD) { |
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originalvalue = rtl_read_dword(rtlpriv, regaddr); |
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bitshift = rtl8723_phy_calculate_bit_shift(bitmask); |
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data = ((originalvalue & (~bitmask)) | (data << bitshift)); |
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} |
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rtl_write_dword(rtlpriv, regaddr, data); |
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rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, |
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"regaddr(%#x), bitmask(%#x), data(%#x)\n", |
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regaddr, bitmask, data); |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_set_bb_reg); |
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u32 rtl8723_phy_calculate_bit_shift(u32 bitmask) |
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{ |
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u32 i = ffs(bitmask); |
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return i ? i - 1 : 32; |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_calculate_bit_shift); |
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u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw, |
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enum radio_path rfpath, u32 offset) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; |
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u32 newoffset; |
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u32 tmplong, tmplong2; |
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u8 rfpi_enable = 0; |
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u32 retvalue; |
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offset &= 0xff; |
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newoffset = offset; |
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if (RT_CANNOT_IO(hw)) { |
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pr_err("return all one\n"); |
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return 0xFFFFFFFF; |
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} |
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tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); |
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if (rfpath == RF90_PATH_A) |
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tmplong2 = tmplong; |
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else |
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tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); |
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tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | |
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(newoffset << 23) | BLSSIREADEDGE; |
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rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, |
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tmplong & (~BLSSIREADEDGE)); |
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rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); |
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rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, |
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tmplong | BLSSIREADEDGE); |
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udelay(120); |
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if (rfpath == RF90_PATH_A) |
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rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, |
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BIT(8)); |
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else if (rfpath == RF90_PATH_B) |
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rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, |
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BIT(8)); |
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if (rfpi_enable) |
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retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, |
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BLSSIREADBACKDATA); |
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else |
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retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, |
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BLSSIREADBACKDATA); |
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rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, |
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"RFR-%d Addr[0x%x]=0x%x\n", |
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rfpath, pphyreg->rf_rb, retvalue); |
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return retvalue; |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_read); |
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void rtl8723_phy_rf_serial_write(struct ieee80211_hw *hw, |
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enum radio_path rfpath, |
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u32 offset, u32 data) |
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{ |
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u32 data_and_addr; |
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u32 newoffset; |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; |
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if (RT_CANNOT_IO(hw)) { |
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pr_err("stop\n"); |
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return; |
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} |
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offset &= 0xff; |
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newoffset = offset; |
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data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; |
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rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); |
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rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, |
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"RFW-%d Addr[0x%x]=0x%x\n", |
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rfpath, pphyreg->rf3wire_offset, |
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data_and_addr); |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_write); |
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long rtl8723_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, |
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enum wireless_mode wirelessmode, |
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u8 txpwridx) |
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{ |
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long offset; |
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long pwrout_dbm; |
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switch (wirelessmode) { |
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case WIRELESS_MODE_B: |
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offset = -7; |
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break; |
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case WIRELESS_MODE_G: |
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case WIRELESS_MODE_N_24G: |
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offset = -8; |
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break; |
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default: |
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offset = -8; |
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break; |
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} |
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pwrout_dbm = txpwridx / 2 + offset; |
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return pwrout_dbm; |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_txpwr_idx_to_dbm); |
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void rtl8723_phy_init_bb_rf_reg_def(struct ieee80211_hw *hw) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; |
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rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; |
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rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; |
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rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; |
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rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; |
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rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; |
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rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; |
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rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; |
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rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; |
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rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; |
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rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; |
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rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; |
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rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = |
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RFPGA0_XA_LSSIPARAMETER; |
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rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = |
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RFPGA0_XB_LSSIPARAMETER; |
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rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; |
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rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; |
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rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; |
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rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; |
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rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; |
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rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; |
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rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; |
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rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; |
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rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; |
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rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; |
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rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; |
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rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; |
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rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; |
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rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; |
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rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; |
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rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; |
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rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; |
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rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; |
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rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; |
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rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; |
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rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; |
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rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; |
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rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; |
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rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; |
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rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; |
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rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; |
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rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE; |
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rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; |
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rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; |
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rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; |
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rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; |
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rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; |
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rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; |
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rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; |
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rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; |
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rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; |
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rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; |
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rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; |
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rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE; |
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rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE; |
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rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; |
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rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; |
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rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; |
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rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; |
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rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK; |
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rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK; |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_init_bb_rf_reg_def); |
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bool rtl8723_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, |
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u32 cmdtableidx, |
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u32 cmdtablesz, |
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enum swchnlcmd_id cmdid, |
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u32 para1, u32 para2, |
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u32 msdelay) |
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{ |
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struct swchnlcmd *pcmd; |
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if (cmdtable == NULL) { |
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WARN_ONCE(true, "rtl8723-common: cmdtable cannot be NULL.\n"); |
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return false; |
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} |
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if (cmdtableidx >= cmdtablesz) |
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return false; |
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pcmd = cmdtable + cmdtableidx; |
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pcmd->cmdid = cmdid; |
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pcmd->para1 = para1; |
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pcmd->para2 = para2; |
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pcmd->msdelay = msdelay; |
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return true; |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_set_sw_chnl_cmdarray); |
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void rtl8723_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, |
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bool iqk_ok, |
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long result[][8], |
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u8 final_candidate, |
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bool btxonly) |
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{ |
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u32 oldval_0, x, tx0_a, reg; |
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long y, tx0_c; |
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if (final_candidate == 0xFF) { |
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return; |
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} else if (iqk_ok) { |
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oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, |
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MASKDWORD) >> 22) & 0x3FF; |
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x = result[final_candidate][0]; |
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if ((x & 0x00000200) != 0) |
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x = x | 0xFFFFFC00; |
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tx0_a = (x * oldval_0) >> 8; |
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rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); |
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rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), |
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((x * oldval_0 >> 7) & 0x1)); |
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y = result[final_candidate][1]; |
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if ((y & 0x00000200) != 0) |
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y = y | 0xFFFFFC00; |
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tx0_c = (y * oldval_0) >> 8; |
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rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, |
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((tx0_c & 0x3C0) >> 6)); |
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rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, |
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(tx0_c & 0x3F)); |
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rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), |
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((y * oldval_0 >> 7) & 0x1)); |
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if (btxonly) |
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return; |
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reg = result[final_candidate][2]; |
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rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); |
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reg = result[final_candidate][3] & 0x3F; |
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rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); |
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reg = (result[final_candidate][3] >> 6) & 0xF; |
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rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); |
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} |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_path_a_fill_iqk_matrix); |
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void rtl8723_save_adda_registers(struct ieee80211_hw *hw, u32 *addareg, |
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u32 *addabackup, u32 registernum) |
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{ |
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u32 i; |
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for (i = 0; i < registernum; i++) |
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addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_save_adda_registers); |
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void rtl8723_phy_save_mac_registers(struct ieee80211_hw *hw, |
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u32 *macreg, u32 *macbackup) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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u32 i; |
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for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) |
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macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); |
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macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_save_mac_registers); |
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void rtl8723_phy_reload_adda_registers(struct ieee80211_hw *hw, |
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u32 *addareg, u32 *addabackup, |
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u32 regiesternum) |
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{ |
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u32 i; |
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for (i = 0; i < regiesternum; i++) |
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rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_reload_adda_registers); |
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void rtl8723_phy_reload_mac_registers(struct ieee80211_hw *hw, |
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u32 *macreg, u32 *macbackup) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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u32 i; |
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for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) |
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rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]); |
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rtl_write_dword(rtlpriv, macreg[i], macbackup[i]); |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_reload_mac_registers); |
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void rtl8723_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg, |
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bool is_patha_on, bool is2t) |
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{ |
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
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u32 pathon; |
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u32 i; |
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if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { |
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pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4; |
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if (!is2t) { |
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pathon = 0x0bdb25a0; |
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rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); |
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} else { |
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rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); |
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} |
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} else { |
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/* rtl8723be */ |
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pathon = 0x01c00014; |
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rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); |
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} |
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for (i = 1; i < IQK_ADDA_REG_NUM; i++) |
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rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon); |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_path_adda_on); |
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void rtl8723_phy_mac_setting_calibration(struct ieee80211_hw *hw, |
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u32 *macreg, u32 *macbackup) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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u32 i = 0; |
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rtl_write_byte(rtlpriv, macreg[i], 0x3F); |
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for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) |
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rtl_write_byte(rtlpriv, macreg[i], |
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(u8) (macbackup[i] & (~BIT(3)))); |
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rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_mac_setting_calibration); |
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|
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void rtl8723_phy_path_a_standby(struct ieee80211_hw *hw) |
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{ |
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rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); |
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rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); |
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rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_path_a_standby); |
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|
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void rtl8723_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode) |
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{ |
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u32 mode; |
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|
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mode = pi_mode ? 0x01000100 : 0x01000000; |
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rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); |
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rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); |
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} |
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EXPORT_SYMBOL_GPL(rtl8723_phy_pi_mode_switch);
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