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596 lines
18 KiB
596 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright(c) 2009-2012 Realtek Corporation.*/ |
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#include "../wifi.h" |
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#include "reg.h" |
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#include "def.h" |
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#include "phy.h" |
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#include "rf.h" |
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#include "dm.h" |
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#include "hw.h" |
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void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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u8 rfpath; |
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switch (bandwidth) { |
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case HT_CHANNEL_WIDTH_20: |
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for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { |
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rtlphy->rfreg_chnlval[rfpath] = ((rtlphy->rfreg_chnlval |
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[rfpath] & 0xfffff3ff) | 0x0400); |
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rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | |
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BIT(11), 0x01); |
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rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, |
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"20M RF 0x18 = 0x%x\n", |
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rtlphy->rfreg_chnlval[rfpath]); |
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} |
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break; |
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case HT_CHANNEL_WIDTH_20_40: |
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for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { |
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rtlphy->rfreg_chnlval[rfpath] = |
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((rtlphy->rfreg_chnlval[rfpath] & 0xfffff3ff)); |
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rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | BIT(11), |
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0x00); |
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rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, |
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"40M RF 0x18 = 0x%x\n", |
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rtlphy->rfreg_chnlval[rfpath]); |
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} |
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break; |
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default: |
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pr_err("unknown bandwidth: %#X\n", bandwidth); |
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break; |
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} |
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} |
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void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, |
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u8 *ppowerlevel) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); |
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struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); |
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u32 tx_agc[2] = {0, 0}, tmpval; |
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bool turbo_scanoff = false; |
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u8 idx1, idx2; |
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u8 *ptr; |
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if (rtlefuse->eeprom_regulatory != 0) |
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turbo_scanoff = true; |
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if (mac->act_scanning) { |
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tx_agc[RF90_PATH_A] = 0x3f3f3f3f; |
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tx_agc[RF90_PATH_B] = 0x3f3f3f3f; |
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if (turbo_scanoff) { |
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for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { |
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tx_agc[idx1] = ppowerlevel[idx1] | |
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(ppowerlevel[idx1] << 8) | |
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(ppowerlevel[idx1] << 16) | |
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(ppowerlevel[idx1] << 24); |
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} |
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} |
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} else { |
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for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { |
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tx_agc[idx1] = ppowerlevel[idx1] | |
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(ppowerlevel[idx1] << 8) | |
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(ppowerlevel[idx1] << 16) | |
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(ppowerlevel[idx1] << 24); |
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} |
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if (rtlefuse->eeprom_regulatory == 0) { |
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tmpval = (rtlphy->mcs_offset[0][6]) + |
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(rtlphy->mcs_offset[0][7] << 8); |
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tx_agc[RF90_PATH_A] += tmpval; |
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tmpval = (rtlphy->mcs_offset[0][14]) + |
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(rtlphy->mcs_offset[0][15] << 24); |
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tx_agc[RF90_PATH_B] += tmpval; |
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} |
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} |
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for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { |
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ptr = (u8 *) (&(tx_agc[idx1])); |
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for (idx2 = 0; idx2 < 4; idx2++) { |
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if (*ptr > RF6052_MAX_TX_PWR) |
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*ptr = RF6052_MAX_TX_PWR; |
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ptr++; |
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} |
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} |
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tmpval = tx_agc[RF90_PATH_A] & 0xff; |
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rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", |
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tmpval, RTXAGC_A_CCK1_MCS32); |
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tmpval = tx_agc[RF90_PATH_A] >> 8; |
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rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", |
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tmpval, RTXAGC_B_CCK11_A_CCK2_11); |
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tmpval = tx_agc[RF90_PATH_B] >> 24; |
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rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", |
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tmpval, RTXAGC_B_CCK11_A_CCK2_11); |
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tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff; |
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rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", |
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tmpval, RTXAGC_B_CCK1_55_MCS32); |
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} |
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static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw, |
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u8 *ppowerlevel, u8 channel, |
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u32 *ofdmbase, u32 *mcsbase) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); |
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u32 powerbase0, powerbase1; |
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u8 legacy_pwrdiff, ht20_pwrdiff; |
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u8 i, powerlevel[2]; |
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for (i = 0; i < 2; i++) { |
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powerlevel[i] = ppowerlevel[i]; |
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legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1]; |
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powerbase0 = powerlevel[i] + legacy_pwrdiff; |
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powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) | |
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(powerbase0 << 8) | powerbase0; |
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*(ofdmbase + i) = powerbase0; |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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" [OFDM power base index rf(%c) = 0x%x]\n", |
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i == 0 ? 'A' : 'B', *(ofdmbase + i)); |
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} |
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for (i = 0; i < 2; i++) { |
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if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) { |
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ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1]; |
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powerlevel[i] += ht20_pwrdiff; |
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} |
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powerbase1 = powerlevel[i]; |
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powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) | |
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(powerbase1 << 8) | powerbase1; |
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*(mcsbase + i) = powerbase1; |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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" [MCS power base index rf(%c) = 0x%x]\n", |
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i == 0 ? 'A' : 'B', *(mcsbase + i)); |
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} |
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} |
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static u8 _rtl92d_phy_get_chnlgroup_bypg(u8 chnlindex) |
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{ |
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u8 group; |
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u8 channel_info[59] = { |
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, |
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36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, |
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60, 62, 64, 100, 102, 104, 106, 108, 110, 112, |
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114, 116, 118, 120, 122, 124, 126, 128, 130, 132, |
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134, 136, 138, 140, 149, 151, 153, 155, 157, 159, |
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161, 163, 165 |
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}; |
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if (channel_info[chnlindex] <= 3) /* Chanel 1-3 */ |
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group = 0; |
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else if (channel_info[chnlindex] <= 9) /* Channel 4-9 */ |
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group = 1; |
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else if (channel_info[chnlindex] <= 14) /* Channel 10-14 */ |
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group = 2; |
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else if (channel_info[chnlindex] <= 64) |
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group = 6; |
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else if (channel_info[chnlindex] <= 140) |
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group = 7; |
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else |
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group = 8; |
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return group; |
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} |
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static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw, |
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u8 channel, u8 index, |
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u32 *powerbase0, |
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u32 *powerbase1, |
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u32 *p_outwriteval) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); |
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u8 i, chnlgroup = 0, pwr_diff_limit[4]; |
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u32 writeval = 0, customer_limit, rf; |
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for (rf = 0; rf < 2; rf++) { |
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switch (rtlefuse->eeprom_regulatory) { |
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case 0: |
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chnlgroup = 0; |
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writeval = rtlphy->mcs_offset |
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[chnlgroup][index + |
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(rf ? 8 : 0)] + ((index < 2) ? |
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powerbase0[rf] : |
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powerbase1[rf]); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"RTK better performance, writeval(%c) = 0x%x\n", |
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rf == 0 ? 'A' : 'B', writeval); |
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break; |
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case 1: |
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if (rtlphy->pwrgroup_cnt == 1) |
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chnlgroup = 0; |
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if (rtlphy->pwrgroup_cnt >= MAX_PG_GROUP) { |
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chnlgroup = _rtl92d_phy_get_chnlgroup_bypg( |
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channel - 1); |
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if (rtlphy->current_chan_bw == |
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HT_CHANNEL_WIDTH_20) |
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chnlgroup++; |
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else |
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chnlgroup += 4; |
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writeval = rtlphy->mcs_offset |
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[chnlgroup][index + |
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(rf ? 8 : 0)] + ((index < 2) ? |
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powerbase0[rf] : |
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powerbase1[rf]); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n", |
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rf == 0 ? 'A' : 'B', writeval); |
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} |
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break; |
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case 2: |
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writeval = ((index < 2) ? powerbase0[rf] : |
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powerbase1[rf]); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"Better regulatory, writeval(%c) = 0x%x\n", |
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rf == 0 ? 'A' : 'B', writeval); |
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break; |
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case 3: |
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chnlgroup = 0; |
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if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"customer's limit, 40MHz rf(%c) = 0x%x\n", |
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rf == 0 ? 'A' : 'B', |
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rtlefuse->pwrgroup_ht40[rf] |
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[channel - 1]); |
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} else { |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"customer's limit, 20MHz rf(%c) = 0x%x\n", |
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rf == 0 ? 'A' : 'B', |
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rtlefuse->pwrgroup_ht20[rf] |
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[channel - 1]); |
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} |
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for (i = 0; i < 4; i++) { |
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pwr_diff_limit[i] = (u8)((rtlphy->mcs_offset |
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[chnlgroup][index + (rf ? 8 : 0)] & |
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(0x7f << (i * 8))) >> (i * 8)); |
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if (rtlphy->current_chan_bw == |
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HT_CHANNEL_WIDTH_20_40) { |
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if (pwr_diff_limit[i] > |
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rtlefuse->pwrgroup_ht40[rf] |
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[channel - 1]) |
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pwr_diff_limit[i] = |
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rtlefuse->pwrgroup_ht40 |
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[rf][channel - 1]; |
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} else { |
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if (pwr_diff_limit[i] > |
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rtlefuse->pwrgroup_ht20[rf][ |
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channel - 1]) |
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pwr_diff_limit[i] = |
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rtlefuse->pwrgroup_ht20[rf] |
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[channel - 1]; |
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} |
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} |
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customer_limit = (pwr_diff_limit[3] << 24) | |
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(pwr_diff_limit[2] << 16) | |
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(pwr_diff_limit[1] << 8) | |
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(pwr_diff_limit[0]); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"Customer's limit rf(%c) = 0x%x\n", |
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rf == 0 ? 'A' : 'B', customer_limit); |
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writeval = customer_limit + ((index < 2) ? |
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powerbase0[rf] : powerbase1[rf]); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"Customer, writeval rf(%c)= 0x%x\n", |
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rf == 0 ? 'A' : 'B', writeval); |
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break; |
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default: |
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chnlgroup = 0; |
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writeval = rtlphy->mcs_offset[chnlgroup][index + |
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(rf ? 8 : 0)] + ((index < 2) ? |
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powerbase0[rf] : powerbase1[rf]); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"RTK better performance, writeval rf(%c) = 0x%x\n", |
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rf == 0 ? 'A' : 'B', writeval); |
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break; |
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} |
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*(p_outwriteval + rf) = writeval; |
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} |
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} |
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static void _rtl92d_write_ofdm_power_reg(struct ieee80211_hw *hw, |
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u8 index, u32 *pvalue) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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static u16 regoffset_a[6] = { |
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RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24, |
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RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04, |
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RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12 |
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}; |
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static u16 regoffset_b[6] = { |
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RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24, |
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RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04, |
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RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12 |
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}; |
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u8 i, rf, pwr_val[4]; |
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u32 writeval; |
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u16 regoffset; |
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for (rf = 0; rf < 2; rf++) { |
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writeval = pvalue[rf]; |
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for (i = 0; i < 4; i++) { |
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pwr_val[i] = (u8) ((writeval & (0x7f << |
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(i * 8))) >> (i * 8)); |
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if (pwr_val[i] > RF6052_MAX_TX_PWR) |
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pwr_val[i] = RF6052_MAX_TX_PWR; |
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} |
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writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) | |
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(pwr_val[1] << 8) | pwr_val[0]; |
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if (rf == 0) |
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regoffset = regoffset_a[index]; |
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else |
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regoffset = regoffset_b[index]; |
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rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"Set 0x%x = %08x\n", regoffset, writeval); |
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if (((get_rf_type(rtlphy) == RF_2T2R) && |
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(regoffset == RTXAGC_A_MCS15_MCS12 || |
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regoffset == RTXAGC_B_MCS15_MCS12)) || |
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((get_rf_type(rtlphy) != RF_2T2R) && |
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(regoffset == RTXAGC_A_MCS07_MCS04 || |
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regoffset == RTXAGC_B_MCS07_MCS04))) { |
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writeval = pwr_val[3]; |
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if (regoffset == RTXAGC_A_MCS15_MCS12 || |
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regoffset == RTXAGC_A_MCS07_MCS04) |
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regoffset = 0xc90; |
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if (regoffset == RTXAGC_B_MCS15_MCS12 || |
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regoffset == RTXAGC_B_MCS07_MCS04) |
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regoffset = 0xc98; |
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for (i = 0; i < 3; i++) { |
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if (i != 2) |
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writeval = (writeval > 8) ? |
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(writeval - 8) : 0; |
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else |
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writeval = (writeval > 6) ? |
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(writeval - 6) : 0; |
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rtl_write_byte(rtlpriv, (u32) (regoffset + i), |
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(u8) writeval); |
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} |
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} |
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} |
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} |
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void rtl92d_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, |
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u8 *ppowerlevel, u8 channel) |
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{ |
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u32 writeval[2], powerbase0[2], powerbase1[2]; |
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u8 index; |
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_rtl92d_phy_get_power_base(hw, ppowerlevel, channel, |
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&powerbase0[0], &powerbase1[0]); |
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for (index = 0; index < 6; index++) { |
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_rtl92d_get_txpower_writeval_by_regulatory(hw, |
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channel, index, &powerbase0[0], |
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&powerbase1[0], &writeval[0]); |
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_rtl92d_write_ofdm_power_reg(hw, index, &writeval[0]); |
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} |
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} |
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bool rtl92d_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); |
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u8 u1btmp; |
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u8 direct = bmac0 ? BIT(3) | BIT(2) : BIT(3); |
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u8 mac_reg = bmac0 ? REG_MAC1 : REG_MAC0; |
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u8 mac_on_bit = bmac0 ? MAC1_ON : MAC0_ON; |
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bool bresult = true; /* true: need to enable BB/RF power */ |
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|
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rtlhal->during_mac0init_radiob = false; |
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rtlhal->during_mac1init_radioa = false; |
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rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "===>\n"); |
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/* MAC0 Need PHY1 load radio_b.txt . Driver use DBI to write. */ |
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u1btmp = rtl_read_byte(rtlpriv, mac_reg); |
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if (!(u1btmp & mac_on_bit)) { |
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rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable BB & RF\n"); |
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/* Enable BB and RF power */ |
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rtl92de_write_dword_dbi(hw, REG_SYS_ISO_CTRL, |
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rtl92de_read_dword_dbi(hw, REG_SYS_ISO_CTRL, direct) | |
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BIT(29) | BIT(16) | BIT(17), direct); |
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} else { |
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/* We think if MAC1 is ON,then radio_a.txt |
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* and radio_b.txt has been load. */ |
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bresult = false; |
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} |
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rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<===\n"); |
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return bresult; |
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|
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} |
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|
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void rtl92d_phy_powerdown_anotherphy(struct ieee80211_hw *hw, bool bmac0) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); |
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u8 u1btmp; |
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u8 direct = bmac0 ? BIT(3) | BIT(2) : BIT(3); |
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u8 mac_reg = bmac0 ? REG_MAC1 : REG_MAC0; |
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u8 mac_on_bit = bmac0 ? MAC1_ON : MAC0_ON; |
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rtlhal->during_mac0init_radiob = false; |
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rtlhal->during_mac1init_radioa = false; |
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rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n"); |
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/* check MAC0 enable or not again now, if |
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* enabled, not power down radio A. */ |
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u1btmp = rtl_read_byte(rtlpriv, mac_reg); |
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if (!(u1btmp & mac_on_bit)) { |
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rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "power down\n"); |
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/* power down RF radio A according to YuNan's advice. */ |
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rtl92de_write_dword_dbi(hw, RFPGA0_XA_LSSIPARAMETER, |
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0x00000000, direct); |
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} |
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rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n"); |
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} |
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|
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bool rtl92d_phy_rf6052_config(struct ieee80211_hw *hw) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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bool rtstatus = true; |
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struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); |
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u32 u4_regvalue = 0; |
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u8 rfpath; |
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struct bb_reg_def *pphyreg; |
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bool mac1_initradioa_first = false, mac0_initradiob_first = false; |
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bool need_pwrdown_radioa = false, need_pwrdown_radiob = false; |
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bool true_bpath = false; |
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|
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if (rtlphy->rf_type == RF_1T1R) |
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rtlphy->num_total_rfpath = 1; |
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else |
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rtlphy->num_total_rfpath = 2; |
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|
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/* Single phy mode: use radio_a radio_b config path_A path_B */ |
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/* seperately by MAC0, and MAC1 needn't configure RF; */ |
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/* Dual PHY mode:MAC0 use radio_a config 1st phy path_A, */ |
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/* MAC1 use radio_b config 2nd PHY path_A. */ |
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/* DMDP,MAC0 on G band,MAC1 on A band. */ |
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if (rtlhal->macphymode == DUALMAC_DUALPHY) { |
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if (rtlhal->current_bandtype == BAND_ON_2_4G && |
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rtlhal->interfaceindex == 0) { |
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/* MAC0 needs PHY1 load radio_b.txt. |
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* Driver use DBI to write. */ |
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if (rtl92d_phy_enable_anotherphy(hw, true)) { |
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rtlphy->num_total_rfpath = 2; |
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mac0_initradiob_first = true; |
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} else { |
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/* We think if MAC1 is ON,then radio_a.txt and |
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* radio_b.txt has been load. */ |
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return rtstatus; |
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} |
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} else if (rtlhal->current_bandtype == BAND_ON_5G && |
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rtlhal->interfaceindex == 1) { |
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/* MAC1 needs PHY0 load radio_a.txt. |
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* Driver use DBI to write. */ |
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if (rtl92d_phy_enable_anotherphy(hw, false)) { |
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rtlphy->num_total_rfpath = 2; |
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mac1_initradioa_first = true; |
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} else { |
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/* We think if MAC0 is ON,then radio_a.txt and |
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* radio_b.txt has been load. */ |
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return rtstatus; |
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} |
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} else if (rtlhal->interfaceindex == 1) { |
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/* MAC0 enabled, only init radia B. */ |
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true_bpath = true; |
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} |
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} |
|
|
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for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { |
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/* Mac1 use PHY0 write */ |
|
if (mac1_initradioa_first) { |
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if (rfpath == RF90_PATH_A) { |
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rtlhal->during_mac1init_radioa = true; |
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need_pwrdown_radioa = true; |
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} else if (rfpath == RF90_PATH_B) { |
|
rtlhal->during_mac1init_radioa = false; |
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mac1_initradioa_first = false; |
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rfpath = RF90_PATH_A; |
|
true_bpath = true; |
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rtlphy->num_total_rfpath = 1; |
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} |
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} else if (mac0_initradiob_first) { |
|
/* Mac0 use PHY1 write */ |
|
if (rfpath == RF90_PATH_A) |
|
rtlhal->during_mac0init_radiob = false; |
|
if (rfpath == RF90_PATH_B) { |
|
rtlhal->during_mac0init_radiob = true; |
|
mac0_initradiob_first = false; |
|
need_pwrdown_radiob = true; |
|
rfpath = RF90_PATH_A; |
|
true_bpath = true; |
|
rtlphy->num_total_rfpath = 1; |
|
} |
|
} |
|
pphyreg = &rtlphy->phyreg_def[rfpath]; |
|
switch (rfpath) { |
|
case RF90_PATH_A: |
|
case RF90_PATH_C: |
|
u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs, |
|
BRFSI_RFENV); |
|
break; |
|
case RF90_PATH_B: |
|
case RF90_PATH_D: |
|
u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs, |
|
BRFSI_RFENV << 16); |
|
break; |
|
} |
|
rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); |
|
udelay(1); |
|
rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); |
|
udelay(1); |
|
/* Set bit number of Address and Data for RF register */ |
|
/* Set 1 to 4 bits for 8255 */ |
|
rtl_set_bbreg(hw, pphyreg->rfhssi_para2, |
|
B3WIREADDRESSLENGTH, 0x0); |
|
udelay(1); |
|
/* Set 0 to 12 bits for 8255 */ |
|
rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); |
|
udelay(1); |
|
switch (rfpath) { |
|
case RF90_PATH_A: |
|
if (true_bpath) |
|
rtstatus = rtl92d_phy_config_rf_with_headerfile( |
|
hw, radiob_txt, |
|
(enum radio_path)rfpath); |
|
else |
|
rtstatus = rtl92d_phy_config_rf_with_headerfile( |
|
hw, radioa_txt, |
|
(enum radio_path)rfpath); |
|
break; |
|
case RF90_PATH_B: |
|
rtstatus = |
|
rtl92d_phy_config_rf_with_headerfile(hw, radiob_txt, |
|
(enum radio_path) rfpath); |
|
break; |
|
case RF90_PATH_C: |
|
break; |
|
case RF90_PATH_D: |
|
break; |
|
} |
|
switch (rfpath) { |
|
case RF90_PATH_A: |
|
case RF90_PATH_C: |
|
rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, |
|
u4_regvalue); |
|
break; |
|
case RF90_PATH_B: |
|
case RF90_PATH_D: |
|
rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16, |
|
u4_regvalue); |
|
break; |
|
} |
|
if (!rtstatus) { |
|
rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, |
|
"Radio[%d] Fail!!\n", rfpath); |
|
goto phy_rf_cfg_fail; |
|
} |
|
|
|
} |
|
|
|
/* check MAC0 enable or not again, if enabled, |
|
* not power down radio A. */ |
|
/* check MAC1 enable or not again, if enabled, |
|
* not power down radio B. */ |
|
if (need_pwrdown_radioa) |
|
rtl92d_phy_powerdown_anotherphy(hw, false); |
|
else if (need_pwrdown_radiob) |
|
rtl92d_phy_powerdown_anotherphy(hw, true); |
|
rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "<---\n"); |
|
return rtstatus; |
|
|
|
phy_rf_cfg_fail: |
|
return rtstatus; |
|
}
|
|
|