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442 lines
13 KiB
442 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright(c) 2009-2012 Realtek Corporation.*/ |
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#include "../wifi.h" |
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#include "reg.h" |
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#include "def.h" |
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#include "phy.h" |
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#include "rf.h" |
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#include "dm.h" |
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static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw); |
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void rtl92cu_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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switch (bandwidth) { |
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case HT_CHANNEL_WIDTH_20: |
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rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] & |
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0xfffff3ff) | 0x0400); |
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rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, |
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rtlphy->rfreg_chnlval[0]); |
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break; |
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case HT_CHANNEL_WIDTH_20_40: |
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rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] & |
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0xfffff3ff)); |
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rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, |
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rtlphy->rfreg_chnlval[0]); |
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break; |
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default: |
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pr_err("unknown bandwidth: %#X\n", bandwidth); |
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break; |
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} |
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} |
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void rtl92cu_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, |
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u8 *ppowerlevel) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); |
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struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); |
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u32 tx_agc[2] = { 0, 0 }, tmpval = 0; |
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u8 idx1, idx2; |
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u8 *ptr; |
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if (mac->act_scanning) { |
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tx_agc[RF90_PATH_A] = 0x3f3f3f3f; |
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tx_agc[RF90_PATH_B] = 0x3f3f3f3f; |
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for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { |
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tx_agc[idx1] = ppowerlevel[idx1] | |
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(ppowerlevel[idx1] << 8) | |
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(ppowerlevel[idx1] << 16) | |
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(ppowerlevel[idx1] << 24); |
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if (tx_agc[idx1] > 0x20 && rtlefuse->external_pa) |
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tx_agc[idx1] = 0x20; |
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} |
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} else { |
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if (rtlpriv->dm.dynamic_txhighpower_lvl == |
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TXHIGHPWRLEVEL_LEVEL1) { |
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tx_agc[RF90_PATH_A] = 0x10101010; |
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tx_agc[RF90_PATH_B] = 0x10101010; |
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} else if (rtlpriv->dm.dynamic_txhighpower_lvl == |
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TXHIGHPWRLEVEL_LEVEL2) { |
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tx_agc[RF90_PATH_A] = 0x00000000; |
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tx_agc[RF90_PATH_B] = 0x00000000; |
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} else { |
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for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { |
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tx_agc[idx1] = ppowerlevel[idx1] | |
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(ppowerlevel[idx1] << 8) | |
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(ppowerlevel[idx1] << 16) | |
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(ppowerlevel[idx1] << 24); |
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} |
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if (rtlefuse->eeprom_regulatory == 0) { |
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tmpval = (rtlphy->mcs_offset[0][6]) + |
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(rtlphy->mcs_offset[0][7] << 8); |
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tx_agc[RF90_PATH_A] += tmpval; |
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tmpval = (rtlphy->mcs_offset[0][14]) + |
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(rtlphy->mcs_offset[0][15] << 24); |
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tx_agc[RF90_PATH_B] += tmpval; |
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} |
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} |
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} |
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for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { |
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ptr = (u8 *) (&(tx_agc[idx1])); |
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for (idx2 = 0; idx2 < 4; idx2++) { |
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if (*ptr > RF6052_MAX_TX_PWR) |
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*ptr = RF6052_MAX_TX_PWR; |
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ptr++; |
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} |
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} |
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tmpval = tx_agc[RF90_PATH_A] & 0xff; |
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rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", |
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tmpval, RTXAGC_A_CCK1_MCS32); |
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tmpval = tx_agc[RF90_PATH_A] >> 8; |
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if (mac->mode == WIRELESS_MODE_B) |
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tmpval = tmpval & 0xff00ffff; |
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rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", |
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tmpval, RTXAGC_B_CCK11_A_CCK2_11); |
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tmpval = tx_agc[RF90_PATH_B] >> 24; |
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rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", |
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tmpval, RTXAGC_B_CCK11_A_CCK2_11); |
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tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff; |
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rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", |
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tmpval, RTXAGC_B_CCK1_55_MCS32); |
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} |
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static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw, |
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u8 *ppowerlevel, u8 channel, |
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u32 *ofdmbase, u32 *mcsbase) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); |
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u32 powerbase0, powerbase1; |
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u8 legacy_pwrdiff = 0, ht20_pwrdiff = 0; |
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u8 i, powerlevel[2]; |
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for (i = 0; i < 2; i++) { |
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powerlevel[i] = ppowerlevel[i]; |
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legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1]; |
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powerbase0 = powerlevel[i] + legacy_pwrdiff; |
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powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) | |
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(powerbase0 << 8) | powerbase0; |
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*(ofdmbase + i) = powerbase0; |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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" [OFDM power base index rf(%c) = 0x%x]\n", |
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i == 0 ? 'A' : 'B', *(ofdmbase + i)); |
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} |
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for (i = 0; i < 2; i++) { |
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if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) { |
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ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1]; |
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powerlevel[i] += ht20_pwrdiff; |
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} |
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powerbase1 = powerlevel[i]; |
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powerbase1 = (powerbase1 << 24) | |
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(powerbase1 << 16) | (powerbase1 << 8) | powerbase1; |
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*(mcsbase + i) = powerbase1; |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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" [MCS power base index rf(%c) = 0x%x]\n", |
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i == 0 ? 'A' : 'B', *(mcsbase + i)); |
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} |
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} |
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static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw, |
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u8 channel, u8 index, |
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u32 *powerbase0, |
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u32 *powerbase1, |
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u32 *p_outwriteval) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); |
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u8 i, chnlgroup = 0, pwr_diff_limit[4]; |
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u32 writeval, customer_limit, rf; |
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for (rf = 0; rf < 2; rf++) { |
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switch (rtlefuse->eeprom_regulatory) { |
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case 0: |
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chnlgroup = 0; |
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writeval = rtlphy->mcs_offset |
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[chnlgroup][index + (rf ? 8 : 0)] |
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+ ((index < 2) ? powerbase0[rf] : powerbase1[rf]); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"RTK better performance,writeval(%c) = 0x%x\n", |
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rf == 0 ? 'A' : 'B', writeval); |
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break; |
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case 1: |
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if (rtlphy->pwrgroup_cnt == 1) |
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chnlgroup = 0; |
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if (rtlphy->pwrgroup_cnt >= 3) { |
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if (channel <= 3) |
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chnlgroup = 0; |
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else if (channel >= 4 && channel <= 9) |
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chnlgroup = 1; |
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else if (channel > 9) |
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chnlgroup = 2; |
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if (rtlphy->current_chan_bw == |
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HT_CHANNEL_WIDTH_20) |
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chnlgroup++; |
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else |
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chnlgroup += 4; |
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} |
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writeval = rtlphy->mcs_offset[chnlgroup][index + |
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(rf ? 8 : 0)] + |
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((index < 2) ? powerbase0[rf] : |
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powerbase1[rf]); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n", |
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rf == 0 ? 'A' : 'B', writeval); |
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break; |
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case 2: |
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writeval = ((index < 2) ? powerbase0[rf] : |
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powerbase1[rf]); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"Better regulatory,writeval(%c) = 0x%x\n", |
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rf == 0 ? 'A' : 'B', writeval); |
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break; |
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case 3: |
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chnlgroup = 0; |
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if (rtlphy->current_chan_bw == |
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HT_CHANNEL_WIDTH_20_40) { |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"customer's limit, 40MHzrf(%c) = 0x%x\n", |
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rf == 0 ? 'A' : 'B', |
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rtlefuse->pwrgroup_ht40[rf] |
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[channel - 1]); |
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} else { |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"customer's limit, 20MHz rf(%c) = 0x%x\n", |
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rf == 0 ? 'A' : 'B', |
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rtlefuse->pwrgroup_ht20[rf] |
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[channel - 1]); |
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} |
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for (i = 0; i < 4; i++) { |
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pwr_diff_limit[i] = (u8) ((rtlphy->mcs_offset |
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[chnlgroup][index + (rf ? 8 : 0)] |
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& (0x7f << (i * 8))) >> (i * 8)); |
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if (rtlphy->current_chan_bw == |
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HT_CHANNEL_WIDTH_20_40) { |
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if (pwr_diff_limit[i] > |
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rtlefuse->pwrgroup_ht40[rf] |
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[channel - 1]) |
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pwr_diff_limit[i] = rtlefuse-> |
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pwrgroup_ht40[rf] |
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[channel - 1]; |
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} else { |
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if (pwr_diff_limit[i] > |
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rtlefuse->pwrgroup_ht20[rf] |
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[channel - 1]) |
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pwr_diff_limit[i] = |
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rtlefuse->pwrgroup_ht20[rf] |
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[channel - 1]; |
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} |
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} |
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customer_limit = (pwr_diff_limit[3] << 24) | |
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(pwr_diff_limit[2] << 16) | |
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(pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"Customer's limit rf(%c) = 0x%x\n", |
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rf == 0 ? 'A' : 'B', customer_limit); |
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writeval = customer_limit + ((index < 2) ? |
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powerbase0[rf] : powerbase1[rf]); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"Customer, writeval rf(%c)= 0x%x\n", |
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rf == 0 ? 'A' : 'B', writeval); |
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break; |
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default: |
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chnlgroup = 0; |
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writeval = rtlphy->mcs_offset[chnlgroup] |
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[index + (rf ? 8 : 0)] + ((index < 2) ? |
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powerbase0[rf] : powerbase1[rf]); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"RTK better performance, writevalrf(%c) = 0x%x\n", |
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rf == 0 ? 'A' : 'B', writeval); |
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break; |
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} |
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if (rtlpriv->dm.dynamic_txhighpower_lvl == |
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TXHIGHPWRLEVEL_LEVEL1) |
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writeval = 0x14141414; |
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else if (rtlpriv->dm.dynamic_txhighpower_lvl == |
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TXHIGHPWRLEVEL_LEVEL2) |
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writeval = 0x00000000; |
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if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1) |
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writeval = writeval - 0x06060606; |
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*(p_outwriteval + rf) = writeval; |
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} |
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} |
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static void _rtl92c_write_ofdm_power_reg(struct ieee80211_hw *hw, |
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u8 index, u32 *value) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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u16 regoffset_a[6] = { |
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RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24, |
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RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04, |
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RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12 |
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}; |
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u16 regoffset_b[6] = { |
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RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24, |
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RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04, |
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RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12 |
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}; |
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u8 i, rf, pwr_val[4]; |
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u32 writeval; |
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u16 regoffset; |
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for (rf = 0; rf < 2; rf++) { |
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writeval = value[rf]; |
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for (i = 0; i < 4; i++) { |
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pwr_val[i] = (u8)((writeval & (0x7f << (i * 8))) >> |
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(i * 8)); |
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if (pwr_val[i] > RF6052_MAX_TX_PWR) |
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pwr_val[i] = RF6052_MAX_TX_PWR; |
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} |
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writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) | |
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(pwr_val[1] << 8) | pwr_val[0]; |
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if (rf == 0) |
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regoffset = regoffset_a[index]; |
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else |
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regoffset = regoffset_b[index]; |
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rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval); |
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR, |
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"Set 0x%x = %08x\n", regoffset, writeval); |
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if (((get_rf_type(rtlphy) == RF_2T2R) && |
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(regoffset == RTXAGC_A_MCS15_MCS12 || |
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regoffset == RTXAGC_B_MCS15_MCS12)) || |
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((get_rf_type(rtlphy) != RF_2T2R) && |
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(regoffset == RTXAGC_A_MCS07_MCS04 || |
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regoffset == RTXAGC_B_MCS07_MCS04))) { |
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writeval = pwr_val[3]; |
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if (regoffset == RTXAGC_A_MCS15_MCS12 || |
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regoffset == RTXAGC_A_MCS07_MCS04) |
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regoffset = 0xc90; |
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if (regoffset == RTXAGC_B_MCS15_MCS12 || |
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regoffset == RTXAGC_B_MCS07_MCS04) |
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regoffset = 0xc98; |
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for (i = 0; i < 3; i++) { |
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if (i != 2) |
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writeval = (writeval > 8) ? |
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(writeval - 8) : 0; |
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else |
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writeval = (writeval > 6) ? |
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(writeval - 6) : 0; |
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rtl_write_byte(rtlpriv, (u32)(regoffset + i), |
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(u8)writeval); |
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} |
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} |
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} |
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} |
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void rtl92cu_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, |
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u8 *ppowerlevel, u8 channel) |
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{ |
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u32 writeval[2], powerbase0[2], powerbase1[2]; |
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u8 index = 0; |
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rtl92c_phy_get_power_base(hw, ppowerlevel, |
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channel, &powerbase0[0], &powerbase1[0]); |
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for (index = 0; index < 6; index++) { |
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_rtl92c_get_txpower_writeval_by_regulatory(hw, |
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channel, index, |
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&powerbase0[0], |
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&powerbase1[0], |
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&writeval[0]); |
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_rtl92c_write_ofdm_power_reg(hw, index, &writeval[0]); |
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} |
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} |
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bool rtl92cu_phy_rf6052_config(struct ieee80211_hw *hw) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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bool rtstatus = true; |
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u8 b_reg_hwparafile = 1; |
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if (rtlphy->rf_type == RF_1T1R) |
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rtlphy->num_total_rfpath = 1; |
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else |
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rtlphy->num_total_rfpath = 2; |
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if (b_reg_hwparafile == 1) |
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rtstatus = _rtl92c_phy_rf6052_config_parafile(hw); |
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return rtstatus; |
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} |
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static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw) |
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{ |
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struct rtl_priv *rtlpriv = rtl_priv(hw); |
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struct rtl_phy *rtlphy = &(rtlpriv->phy); |
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u32 u4_regvalue = 0; |
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u8 rfpath; |
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bool rtstatus = true; |
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struct bb_reg_def *pphyreg; |
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for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { |
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pphyreg = &rtlphy->phyreg_def[rfpath]; |
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switch (rfpath) { |
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case RF90_PATH_A: |
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case RF90_PATH_C: |
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u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs, |
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BRFSI_RFENV); |
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break; |
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case RF90_PATH_B: |
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case RF90_PATH_D: |
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u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs, |
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BRFSI_RFENV << 16); |
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break; |
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} |
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rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); |
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udelay(1); |
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rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); |
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udelay(1); |
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rtl_set_bbreg(hw, pphyreg->rfhssi_para2, |
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B3WIREADDREAALENGTH, 0x0); |
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udelay(1); |
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rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); |
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udelay(1); |
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switch (rfpath) { |
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case RF90_PATH_A: |
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case RF90_PATH_B: |
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rtstatus = rtl92cu_phy_config_rf_with_headerfile(hw, |
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(enum radio_path) rfpath); |
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break; |
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case RF90_PATH_C: |
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break; |
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case RF90_PATH_D: |
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break; |
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} |
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switch (rfpath) { |
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case RF90_PATH_A: |
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case RF90_PATH_C: |
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rtl_set_bbreg(hw, pphyreg->rfintfs, |
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BRFSI_RFENV, u4_regvalue); |
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break; |
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case RF90_PATH_B: |
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case RF90_PATH_D: |
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rtl_set_bbreg(hw, pphyreg->rfintfs, |
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BRFSI_RFENV << 16, u4_regvalue); |
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break; |
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} |
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if (!rtstatus) { |
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rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, |
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"Radio[%d] Fail!!\n", rfpath); |
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goto phy_rf_cfg_fail; |
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} |
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} |
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rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "<---\n"); |
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phy_rf_cfg_fail: |
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return rtstatus; |
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}
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