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302 lines
8.2 KiB
302 lines
8.2 KiB
/* @file mwifiex_pcie.h |
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* |
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* @brief This file contains definitions for PCI-E interface. |
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* driver. |
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* |
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* Copyright 2011-2020 NXP |
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* |
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* This software file (the "File") is distributed by NXP |
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* under the terms of the GNU General Public License Version 2, June 1991 |
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* (the "License"). You may use, redistribute and/or modify this File in |
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* accordance with the terms and conditions of the License, a copy of which |
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* is available by writing to the Free Software Foundation, Inc., |
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the |
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* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. |
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* |
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* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE |
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* ARE EXPRESSLY DISCLAIMED. The License provides additional details about |
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* this warranty disclaimer. |
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*/ |
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#ifndef _MWIFIEX_PCIE_H |
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#define _MWIFIEX_PCIE_H |
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#include <linux/completion.h> |
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#include <linux/pci.h> |
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#include <linux/interrupt.h> |
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#include "decl.h" |
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#include "main.h" |
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#define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin" |
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#define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin" |
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#define PCIE8897_A0_FW_NAME "mrvl/pcie8897_uapsta_a0.bin" |
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#define PCIE8897_B0_FW_NAME "mrvl/pcie8897_uapsta.bin" |
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#define PCIEUART8997_FW_NAME_V4 "mrvl/pcieuart8997_combo_v4.bin" |
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#define PCIEUSB8997_FW_NAME_V4 "mrvl/pcieusb8997_combo_v4.bin" |
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#define PCIE_VENDOR_ID_MARVELL (0x11ab) |
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#define PCIE_VENDOR_ID_V2_MARVELL (0x1b4b) |
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#define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30) |
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#define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38) |
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#define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42) |
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#define PCIE8897_A0 0x1100 |
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#define PCIE8897_B0 0x1200 |
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#define PCIE8997_A0 0x10 |
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#define PCIE8997_A1 0x11 |
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#define CHIP_VER_PCIEUART 0x3 |
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#define CHIP_MAGIC_VALUE 0x24 |
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/* Constants for Buffer Descriptor (BD) rings */ |
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#define MWIFIEX_MAX_TXRX_BD 0x20 |
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#define MWIFIEX_TXBD_MASK 0x3F |
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#define MWIFIEX_RXBD_MASK 0x3F |
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#define MWIFIEX_MAX_EVT_BD 0x08 |
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#define MWIFIEX_EVTBD_MASK 0x0f |
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/* PCIE INTERNAL REGISTERS */ |
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#define PCIE_SCRATCH_0_REG 0xC10 |
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#define PCIE_SCRATCH_1_REG 0xC14 |
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#define PCIE_CPU_INT_EVENT 0xC18 |
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#define PCIE_CPU_INT_STATUS 0xC1C |
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#define PCIE_HOST_INT_STATUS 0xC30 |
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#define PCIE_HOST_INT_MASK 0xC34 |
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#define PCIE_HOST_INT_STATUS_MASK 0xC3C |
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#define PCIE_SCRATCH_2_REG 0xC40 |
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#define PCIE_SCRATCH_3_REG 0xC44 |
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#define PCIE_SCRATCH_4_REG 0xCD0 |
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#define PCIE_SCRATCH_5_REG 0xCD4 |
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#define PCIE_SCRATCH_6_REG 0xCD8 |
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#define PCIE_SCRATCH_7_REG 0xCDC |
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#define PCIE_SCRATCH_8_REG 0xCE0 |
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#define PCIE_SCRATCH_9_REG 0xCE4 |
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#define PCIE_SCRATCH_10_REG 0xCE8 |
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#define PCIE_SCRATCH_11_REG 0xCEC |
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#define PCIE_SCRATCH_12_REG 0xCF0 |
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#define PCIE_SCRATCH_13_REG 0xCF4 |
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#define PCIE_SCRATCH_14_REG 0xCF8 |
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#define PCIE_SCRATCH_15_REG 0xCFC |
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#define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C |
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#define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C |
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#define CPU_INTR_DNLD_RDY BIT(0) |
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#define CPU_INTR_DOOR_BELL BIT(1) |
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#define CPU_INTR_SLEEP_CFM_DONE BIT(2) |
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#define CPU_INTR_RESET BIT(3) |
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#define CPU_INTR_EVENT_DONE BIT(5) |
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#define HOST_INTR_DNLD_DONE BIT(0) |
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#define HOST_INTR_UPLD_RDY BIT(1) |
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#define HOST_INTR_CMD_DONE BIT(2) |
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#define HOST_INTR_EVENT_RDY BIT(3) |
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#define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \ |
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HOST_INTR_UPLD_RDY | \ |
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HOST_INTR_CMD_DONE | \ |
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HOST_INTR_EVENT_RDY) |
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#define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7) |
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#define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0) |
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#define MWIFIEX_BD_FLAG_LAST_DESC BIT(1) |
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#define MWIFIEX_BD_FLAG_SOP BIT(0) |
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#define MWIFIEX_BD_FLAG_EOP BIT(1) |
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#define MWIFIEX_BD_FLAG_XS_SOP BIT(2) |
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#define MWIFIEX_BD_FLAG_XS_EOP BIT(3) |
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#define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7) |
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#define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10) |
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#define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16) |
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#define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26) |
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/* Max retry number of command write */ |
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#define MAX_WRITE_IOMEM_RETRY 2 |
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/* Define PCIE block size for firmware download */ |
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#define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256 |
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/* FW awake cookie after FW ready */ |
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#define FW_AWAKE_COOKIE (0xAA55AA55) |
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#define MWIFIEX_DEF_SLEEP_COOKIE 0xBEEFBEEF |
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#define MWIFIEX_SLEEP_COOKIE_SIZE 4 |
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#define MWIFIEX_MAX_DELAY_COUNT 100 |
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#define MWIFIEX_PCIE_FLR_HAPPENS 0xFEDCBABA |
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struct mwifiex_pcie_card_reg { |
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u16 cmd_addr_lo; |
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u16 cmd_addr_hi; |
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u16 fw_status; |
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u16 cmd_size; |
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u16 cmdrsp_addr_lo; |
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u16 cmdrsp_addr_hi; |
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u16 tx_rdptr; |
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u16 tx_wrptr; |
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u16 rx_rdptr; |
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u16 rx_wrptr; |
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u16 evt_rdptr; |
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u16 evt_wrptr; |
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u16 drv_rdy; |
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u16 tx_start_ptr; |
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u32 tx_mask; |
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u32 tx_wrap_mask; |
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u32 rx_mask; |
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u32 rx_wrap_mask; |
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u32 tx_rollover_ind; |
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u32 rx_rollover_ind; |
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u32 evt_rollover_ind; |
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u8 ring_flag_sop; |
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u8 ring_flag_eop; |
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u8 ring_flag_xs_sop; |
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u8 ring_flag_xs_eop; |
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u32 ring_tx_start_ptr; |
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u8 pfu_enabled; |
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u8 sleep_cookie; |
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u16 fw_dump_ctrl; |
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u16 fw_dump_start; |
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u16 fw_dump_end; |
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u8 fw_dump_host_ready; |
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u8 fw_dump_read_done; |
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u8 msix_support; |
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}; |
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struct mwifiex_pcie_device { |
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const struct mwifiex_pcie_card_reg *reg; |
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u16 blksz_fw_dl; |
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u16 tx_buf_size; |
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bool can_dump_fw; |
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struct memory_type_mapping *mem_type_mapping_tbl; |
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u8 num_mem_types; |
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bool can_ext_scan; |
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}; |
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struct mwifiex_evt_buf_desc { |
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u64 paddr; |
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u16 len; |
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u16 flags; |
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} __packed; |
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struct mwifiex_pcie_buf_desc { |
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u64 paddr; |
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u16 len; |
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u16 flags; |
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} __packed; |
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struct mwifiex_pfu_buf_desc { |
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u16 flags; |
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u16 offset; |
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u16 frag_len; |
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u16 len; |
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u64 paddr; |
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u32 reserved; |
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} __packed; |
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#define MWIFIEX_NUM_MSIX_VECTORS 4 |
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struct mwifiex_msix_context { |
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struct pci_dev *dev; |
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u16 msg_id; |
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}; |
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struct pcie_service_card { |
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struct pci_dev *dev; |
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struct mwifiex_adapter *adapter; |
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struct mwifiex_pcie_device pcie; |
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struct completion fw_done; |
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u8 txbd_flush; |
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u32 txbd_wrptr; |
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u32 txbd_rdptr; |
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u32 txbd_ring_size; |
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u8 *txbd_ring_vbase; |
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dma_addr_t txbd_ring_pbase; |
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void *txbd_ring[MWIFIEX_MAX_TXRX_BD]; |
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struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD]; |
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u32 rxbd_wrptr; |
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u32 rxbd_rdptr; |
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u32 rxbd_ring_size; |
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u8 *rxbd_ring_vbase; |
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dma_addr_t rxbd_ring_pbase; |
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void *rxbd_ring[MWIFIEX_MAX_TXRX_BD]; |
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struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD]; |
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u32 evtbd_wrptr; |
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u32 evtbd_rdptr; |
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u32 evtbd_ring_size; |
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u8 *evtbd_ring_vbase; |
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dma_addr_t evtbd_ring_pbase; |
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void *evtbd_ring[MWIFIEX_MAX_EVT_BD]; |
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struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD]; |
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struct sk_buff *cmd_buf; |
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struct sk_buff *cmdrsp_buf; |
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u8 *sleep_cookie_vbase; |
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dma_addr_t sleep_cookie_pbase; |
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void __iomem *pci_mmap; |
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void __iomem *pci_mmap1; |
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int msi_enable; |
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int msix_enable; |
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#ifdef CONFIG_PCI |
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struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS]; |
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#endif |
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struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS]; |
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struct mwifiex_msix_context share_irq_ctx; |
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struct work_struct work; |
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unsigned long work_flags; |
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bool pci_reset_ongoing; |
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unsigned long quirks; |
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}; |
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static inline int |
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mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr) |
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{ |
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const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
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switch (card->dev->device) { |
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case PCIE_DEVICE_ID_MARVELL_88W8766P: |
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if (((card->txbd_wrptr & reg->tx_mask) == |
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(rdptr & reg->tx_mask)) && |
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((card->txbd_wrptr & reg->tx_rollover_ind) != |
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(rdptr & reg->tx_rollover_ind))) |
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return 1; |
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break; |
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case PCIE_DEVICE_ID_MARVELL_88W8897: |
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case PCIE_DEVICE_ID_MARVELL_88W8997: |
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if (((card->txbd_wrptr & reg->tx_mask) == |
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(rdptr & reg->tx_mask)) && |
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((card->txbd_wrptr & reg->tx_rollover_ind) == |
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(rdptr & reg->tx_rollover_ind))) |
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return 1; |
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break; |
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} |
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return 0; |
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} |
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static inline int |
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mwifiex_pcie_txbd_not_full(struct pcie_service_card *card) |
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{ |
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const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
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switch (card->dev->device) { |
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case PCIE_DEVICE_ID_MARVELL_88W8766P: |
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if (((card->txbd_wrptr & reg->tx_mask) != |
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(card->txbd_rdptr & reg->tx_mask)) || |
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((card->txbd_wrptr & reg->tx_rollover_ind) != |
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(card->txbd_rdptr & reg->tx_rollover_ind))) |
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return 1; |
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break; |
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case PCIE_DEVICE_ID_MARVELL_88W8897: |
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case PCIE_DEVICE_ID_MARVELL_88W8997: |
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if (((card->txbd_wrptr & reg->tx_mask) != |
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(card->txbd_rdptr & reg->tx_mask)) || |
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((card->txbd_wrptr & reg->tx_rollover_ind) == |
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(card->txbd_rdptr & reg->tx_rollover_ind))) |
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return 1; |
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break; |
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} |
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return 0; |
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} |
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#endif /* _MWIFIEX_PCIE_H */
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